Vinay B. Y. Kumar - researchr alias

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Viewing Publication 1 - 19 from 19

2022

AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based AcceleratorsSimei Yang, Debjyoti Bhattacharjee, Vinay B. Y. Kumar, Saikat Chatterjee, Sayandip De, Peter Debacker, Diederik Verkest, Arindam Mallik, Francky Catthoor. esticas, 12(2):508-521, 2022. [doi]

2021

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault AttacksAnubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar. date 2021: 561-564 [doi]

2020

A Novel Duplication Based Countermeasure to Statistical Ineffective Fault AnalysisAnubhab Baksi, Vinay B. Y. Kumar, Banashri Karmakar, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay. acisp 2020: 525-542 [doi]

A Novel Duplication Based Countermeasure To Statistical Ineffective Fault AnalysisAnubhab Baksi, Vinay B. Y. Kumar, Banashri Karmakar, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay. iacr, 2020:1268, 2020. [doi]

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version)Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar. iacr, 2020:1542, 2020. [doi]

Secure Your SoC: Building System-an-Chip Designs for SecurityShivam Bhasin, Trevor E. Carlson, Anupam Chattopadhyay, Vinay B. Y. Kumar, Avi Mendelson, Romain Poussier, Yaswanth Tavva. socc 2020: 248-253 [doi]

Post-Quantum Secure BootVinay B. Y. Kumar, Naina Gupta 0001, Anupam Chattopadhyay, Michael Kasper, Christoph Krauß, Ruben Niederhagen. date 2020: 1582-1585 [doi]

Towards Designing a Secure RISC-V System-on-Chip: ITUSVinay B. Y. Kumar, Suman Deb, Naina Gupta 0001, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, Avi Mendelson. jhss, 4(4):329-342, 2020. [doi]

2019

ITUS: A Secure RISC-V System-on-ChipVinay B. Y. Kumar, Anupam Chattopadhyay, Jawad Haj-Yahya, Avi Mendelson. socc 2019: 418-423 [doi]

Recruiting Fault Tolerance Techniques for Microprocessor SecurityVinay B. Y. Kumar, Suman Deb, Rupesh Kumar, Mustafa Khairallah, Anupam Chattopadhyay, Avi Mendelson. ats 2019: 80-85 [doi]

2018

Lightweight Forth Programmable NoCsVinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar. vlsid 2018: 368-373 [doi]

2016

Relaxation Based Circuit Simulation Acceleration over CPU-FPGAVinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar. vlsid 2016: 409-414 [doi]

2015

Parallel two step random walk algorithm to analyze VLSI power grid networksSatyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar. vdat 2015: 1-2 [doi]

2014

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototypingVinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar. iccd 2014: 464-469 [doi]

FPGA-based implementation of M4RM for matrix multiplication over GF(2)Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar. vdat 2014: 1-2 [doi]

Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systemsJanak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar. vlsi-dat 2014: 1-4 [doi]

2013

Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois FieldsPrateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar. peccs 2013: 195-201

2010

FPGA Based High Performance Double-Precision Matrix MultiplicationVinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan. ijpp, 38(3-4):322-338, 2010. [doi]

2009

FPGA Based High Performance Double-Precision Matrix MultiplicationVinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan. vlsid 2009: 341-346 [doi]

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