Vincenzo Rana - researchr alias

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Viewing Publication 1 - 61 from 61

2022

A Protocol for On-Chain TendersFrancesco Bruschi, Tommaso Paulon, Vincenzo Rana, Donatella Sciuto. percom 2022: 273-278 [doi]

2021

A privacy preserving identification protocol for smart contractsFrancesco Bruschi, Tommaso Paulon, Vincenzo Rana, Donatella Sciuto. ISCC 2021: 1-6 [doi]

Tunneling Trust Into the Blockchain: A Merkle Based Proof System for Structured DocumentsFrancesco Bruschi, Vincenzo Rana, Alessio Pagani, Donatella Sciuto. access, 9:103758-103771, 2021. [doi]

2020

Acknowledging Value of Personal Information: a Privacy Aware Data Market for Health and Social ResearchFrancesco Bruschi, Vincenzo Rana, Alessio Pagani, Donatella Sciuto. itasec 2020: [doi]

A Decentralized System for Fair Token Distribution and Seamless Users OnboardingFrancesco Bruschi, Manuel Tumiati, Vincenzo Rana, Mattia Bianchi, Donatella Sciuto. ISCC 2020: 1-6 [doi]

2018

Mine with it or sell it: the superhashing power dilemmaFrancesco Bruschi, Vincenzo Rana, Lorenzo Gentile, Donatella Sciuto. sigmetrics, 46(3):127-130, 2018. [doi]

BuildingRules: A Trigger-Action-Based System to Manage Complex Commercial BuildingsAlessandro Antonio Nacci, Vincenzo Rana, Bharathan Balaji, Paola Spoletini, Rajesh E. Gupta, Donatella Sciuto, Yuvraj Agarwal. tcps, 2(2), 2018. [doi]

2017

2016

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA DevicesIvan Beretta, Vincenzo Rana, Abdulkadir Akin, Alessandro Antonio Nacci, Donatella Sciuto, David Atienza. tecs, 15(3):44, 2016. [doi]

Reconstruction of public transport stateAlessio Pagani, Francesco Bruschi, Vincenzo Rana, Marcello Restelli. itsc 2016: 2285-2292 [doi]

Ruleset Minimization in Multi-tenant Smart BuildingsAndrea Piscitello, Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. cse 2016: 72-79 [doi]

Sink state analysis in multi-tenant smart buildingsAndrea Piscitello, Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. rtsi 2016: 1-4 [doi]

Efficient Hardware Design of Iterative Stencil LoopsVincenzo Rana, Ivan Beretta, Francesco Bruschi, Alessandro Antonio Nacci, David Atienza, Donatella Sciuto. tcad, 35(12):2018-2031, 2016. [doi]

2014

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable PlatformsJuan Antonio Clemente, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto. trets, 7(2):9, 2014. [doi]

BlueSentinel: a first approach using iBeacon for an energy efficient occupancy detection systemGiorgio Conte, Massimo De Marchi, Alessandro Antonio Nacci, Vincenzo Rana, Donatella Sciuto. sensys 2014: 11-19 [doi]

A SystemC-based framework for the simulation of appliances networks in energy-aware smart spacesA. A. Nacci, G. Bettinazzi, Christian Pilato, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. In WF-IoT. 2014: 485-490 [doi]

An Open-Source, Efficient, and Parameterizable Hardware Implementation of the AES AlgorithmAlessandro Antonio Nacci, Vincenzo Rana, Donatella Sciuto, Marco Domenico Santambrogio. ispa 2014: 85-92 [doi]

Improving the security and the scalability of the AES algorithm (abstract only)Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. fpga 2014: 256 [doi]

A Perspective Vision on Complex Residential Building Management SystemsAlessandro Antonio Nacci, Vincenzo Rana, Donatella Sciuto. euc 2014: 209-214 [doi]

On How to Efficiently Implement Regular Expression Matching on FPGA-Based SystemsVincenzo Rana, Francesco Bruschi, Marco Paolieri, Donatella Sciuto, Marco Domenico Santambrogio. euc 2014: 304-309 [doi]

2013

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devicesAlessandro Antonio Nacci, Vincenzo Rana, Francesco Bruschi, Donatella Sciuto, Ivan Beretta, David Atienza. dac 2013: 52 [doi]

Design Methods for Parallel Hardware Implementation of Multimedia Iterative AlgorithmsVincenzo Rana, Alessandro Antonio Nacci, Ivan Beretta, Marco D. Santambrogio, David Atienza, Donatella Sciuto. dt, 30(4):71-80, 2013. [doi]

2012

Design exploration of energy-performance trade-offs for wireless sensor networksIvan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza. dac 2012: 1043-1048 [doi]

Model-based design for wireless body sensor network nodesIvan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza, Donatella Sciuto. latw 2012: 1-6 [doi]

2IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor NetworksPaolo Roberto Grassi, Vincenzo Rana, Ivan Beretta, Donatella Sciuto. bsn 2012: 46-51 [doi]

Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor NetworksPaolo Roberto Grassi, Vincenzo Rana, Ivan Beretta, Donatella Sciuto. dsd 2012: 874-881 [doi]

Knowledge-based design space exploration of wireless sensor networksPaolo Roberto Grassi, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto. codes 2012: 225-234 [doi]

2011

A high-performance parallel implementation of the Chambolle algorithmA. Akin, Ivan Beretta, A. A. Nacci, Vincenzo Rana, Marco D. Santambrogio, David Atienza. date 2011: 1436-1441 [doi]

Island-Based Adaptable Embedded System DesignIvan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto. esl, 3(2):53-57, 2011. [doi]

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip DesignIvan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto. tcad, 30(8):1211-1224, 2011. [doi]

On-chip network resource management design and validationFrancesco Bruschi, Antonio Miele, Vincenzo Rana. samos 2011: 249-254 [doi]

An efficient Quantum-Dot Cellular Automata adderFrancesco Bruschi, Francesco Perini, Vincenzo Rana, Donatella Sciuto. date 2011: 1220-1223 [doi]

A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable HardwareJuan Antonio Clemente, Vincenzo Rana, Donatella Sciuto, Ivan Beretta, David Atienza. fpl 2011: 177-180 [doi]

2010

2009

2008

An architecture for dynamically reconfigurable real time audio processing systemsFrancesco Bruschi, Vincenzo Rana, Donatella Sciuto. estimedia 2008: 81-86 [doi]

A light-weight Network-on-Chip architecture for dynamically reconfigurable systemsSimone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. samos 2008: 49-56 [doi]

A Generation Flow for Self-Reconfiguration Controllers CustomizationAndrea Cuoccio, Paolo R. Grassi, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. delta 2008: 279-284 [doi]

The Shining embedded system design methodology based on self dynamic reconfigurable architecturesCarlo Curino, Luca Fossati, Vincenzo Rana, Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto. aspdac 2008: 595-600 [doi]

A Requirements-Driven Simulation Framework for Communication Infrastructures DesignAlessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Francesco Bruschi. fdl 2008: 111-117 [doi]

Design of Communication Infrastructures for Reconfigurable SystemsAlessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Francesco Bruschi. fdl 2009: 291-307 [doi]

A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design FlowAlessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. delta 2008: 405-409 [doi]

HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architecturesAlessio Montone, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. ipps 2008: 1-8 [doi]

Low cost smartcams designVincenzo Rana, Matteo Matteucci, Daniele Caltabiano, Roberto Sannino, Andrea Bonarini. estimedia 2008: 27-32 [doi]

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC CommunicationVincenzo Rana, David Atienza, Marco D. Santambrogio, Donatella Sciuto, Giovanni De Micheli. vlsi 2010: 232-250 [doi]

Operating system support for online partial dynamic reconfiguration managementMarco D. Santambrogio, Vincenzo Rana, Donatella Sciuto. fpl 2008: 455-458 [doi]

2007

Dynamic Reconfigurability in Embedded System DesignVincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. iscas 2007: 2734-2737 [doi]

An adaptive genetic algorithm for dynamically reconfigurable modules allocationVincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto. vlsi 2009: 1-18 [doi]

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on LinuxVincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert. ipps 2007: 1-8 [doi]

An adaptive genetic algorithm for dynamically reconfigurable modules allocationVincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto. vlsi 2007: 128-133 [doi]

A novel SoC design methodology combining adaptive software and reconfigurable hardwareMarco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto. iccad 2007: 303-308 [doi]

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