Walid A. Najjar - researchr alias

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2011

Massively parallel XML twig filtering using dynamic programming on FPGAsRoger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras. icde 2011: 948-959 [doi]

2010

2009

2008

Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAsBetul Buyukkurt, Walid A. Najjar. fpl 2008: 655-658 [doi]

Efficient hardware code generation for FPGAsZhi Guo, Walid A. Najjar, Betul Buyukkurt. taco, 5(1), 2008. [doi]

A Compiler Intermediate Representation for Reconfigurable FabricsZhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar. ijpp, 36(5):493-520, 2008. [doi]

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2008), Samos, Greece, July 21-24, 2008Walid A. Najjar, Holger Blume, editors, IEEE, 2008.

Compiled hardware acceleration of Molecular Dynamics codeJason R. Villarreal, Walid A. Najjar. fpl 2008: 667-670 [doi]

OpenFPGA CoreLib core library interoperability effortMichael J. Wirthlin, Daniel S. Poznanovic, P. Sundararajan, Alan J. Coppola, D. Pellerin, Walid A. Najjar, R. Bruce, M. Babst, O. Pritchard, Paolo Palazzari, Georgi Kuzmanov. pc, 34(4-5):231-244, 2008. [doi]

OpenFPGA CoreLib core library interoperability effortMichael J. Wirthlin, Daniel S. Poznanovic, P. Sundararajan, Alan J. Coppola, D. Pellerin, Walid A. Najjar, R. Bruce, M. Babst, O. Pritchard, Paolo Palazzari, Georgi Kuzmanov. pc, 34(4-5):231-244, 2008. [doi]

2007

FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, Stamatis Vassiliadis, editors, IEEE, 2007.

A one-shot configurable-cache tuner for improved energy and performanceAnn Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros. date 2007: 755-760 [doi]

Compiling PCRE to FPGA for accelerating SNORT IDSAbhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan. ancs 2007: 127-136 [doi]

Compiling code accelerators for FPGAsWalid A. Najjar. codes 2007: 2 [doi]

Compiling code accelerators for FPGAsWalid A. Najjar. cases 2007: 1-2 [doi]

Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor SystemKai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid. fpl 2007: 533-536 [doi]

2006

Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAsBetul Buyukkurt, Zhi Guo, Walid A. Najjar. arc 2006: 401-412 [doi]

Automation of IP Core Interface Generation for Reconfigurable ComputingZhi Guo, Abhishek Mitra, Walid A. Najjar. fpl 2006: 1-6 [doi]

A Compiler Intermediate Representation for Reconfigurable FabricsZhi Guo, Walid A. Najjar. fpl 2006: 1-4 [doi]

Compile-time area estimation for LUT-based FPGAsDhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi. todaes, 11(1):104-122, 2006. [doi]

Efficient indexing data structures for flash-based sensor devicesSong Lin, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar. tos, 2(4):468-503, 2006. [doi]

Dynamic Co-Processor Architecture for Software Acceleration on CSoCsAbhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar. iccd 2006: [doi]

A code refinement methodology for performance-improved synthesis from CGreg Stitt, Frank Vahid, Walid A. Najjar. iccad 2006: 716-723 [doi]

Automatic Compilation Framework for Bloom Filter Based Intrusion DetectionDinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar. arc 2006: 413-418 [doi]

2005

Splitting the sensor nodeAnirban Banerjee, Anirban Mitra, Walid A. Najjar. sensys 2005: 270-271 [doi]

Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005Thomas M. Conte, Paolo Faraboschi, William H. Mangione-Smith, Walid A. Najjar, editors, ACM, 2005.

Optimized Generation of Data-Path from C Codes for FPGAsZhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers. date 2005: 112-117 [doi]

Techniques for synthesizing binaries to an advanced register/memory structureGreg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid. fpga 2005: 118-124 [doi]

VALVE: Variable Length Value Encoder for Off-Chip Data Buses.Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang. iccd 2005: 631-633 [doi]

Power Efficient Instruction Caches for Embedded SystemsDinesh C. Suresh, Walid A. Najjar, Jun Yang. samos 2005: 182-191 [doi]

A tunable bus encoder for off-chip data busesDinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar. islped 2005: 319-322 [doi]

Data Acquisition in Sensor Networks with Large MemoriesDemetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar. icde 2005: 1188 [doi]

Towards In-Situ Data Storage in Sensor DatabasesDemetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Anirban Mitra, Anirban Banerjee, Walid A. Najjar. pci 2005: 36-46 [doi]

MicroHash: An Efficient Index Structure for Flash-Based Sensor DevicesDemetrios Zeinalipour-Yazti, Song Lin, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar. FAST 2005: [doi]

A way-halting cache for low-energy high-performance systemsChuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. taco, 2(1):34-54, 2005. [doi]

A highly configurable cache for low energy embedded systemsChuanjun Zhang, Frank Vahid, Walid A. Najjar. tecs, 4(2):363-387, 2005. [doi]

2004

2003

First results with eBlocks: embedded systems building blocksSusan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh. codes 2003: 168-175 [doi]

High-Level Language Abstraction for Reconfigurable ComputingWalid A. Najjar, A. P. Wim Böhm, Bruce A. Draper, Jeffrey Hammes, Robert Rinker, J. Ross Beveridge, Monica Chawathe, Charles Ross. Computer, 36(8):63-69, 2003. [doi]

Power efficient encoding techniques for off-chip data busesDinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan. cases 2003: 267-275 [doi]

FV-MSB: A Scheme for Reducing Transition Activity on Data BusesDinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar. hipc 2003: 44-54 [doi]

Profiling tools for hardware/software partitioning of embedded applicationsDinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt. lctrts 2003: 189-198 [doi]

Automatic compilation to a coarse-grained reconfigurable system-opn-chipGirish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes. tecs, 2(4):560-589, 2003. [doi]

Energy Benefits of a Configurable Line Size Cache for Embedded SystemsChuanjun Zhang, Frank Vahid, Walid A. Najjar. isvlsi 2003: 87-91 [doi]

A Way-Halting Cache for Low-Energy High-Performance SystemsChuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. cal, 2, 2003. [doi]

A Highly-Configurable Cache Architecture for Embedded SystemsChuanjun Zhang, Frank Vahid, Walid A. Najjar. isca 2003: 136-146 [doi]

2002

2001

Compiling SA-C Programs to FPGAs: Performance ResultsBruce A. Draper, A. P. Wim Böhm, Jeffrey Hammes, Walid A. Najjar, J. Ross Beveridge, Charlie Ross, Monica Chawathe, Mitesh Desai, José Bins. icvs 2001: 220-235 [doi]

The Sisal Project: Real World Functional ProgrammingJean-Luc Gaudiot, Thomas DeBoni, John Feo, A. P. Wim Böhm, Walid A. Najjar, Patrick Miller. cosps 2001: 45-72 [doi]

Loop fusion and temporal common subexpression elimination in window-based loopsJeffrey Hammes, A. P. Wim Böhm, Charlie Ross, Monica Chawathe, Bruce A. Draper, Robert Rinker, Walid A. Najjar. ipps 2001: 142

Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubesDianne R. Kumar, Walid A. Najjar, Pradip K. Srimani. ipps 2001: 160

A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-CubesDianne R. Kumar, Walid A. Najjar, Pradip K. Srimani. TC, 50(7):647-659, 2001. [doi]

An automated process for compiling dataflow graphs into reconfigurable hardwareRobert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm. tvlsi, 9(1):130-139, 2001. [doi]

Resource Management in Dataflow-Based Multithreaded ExecutionLucas Roh, Bhanu Shankar, A. P. Wim Böhm, Walid A. Najjar. jpdc, 61(5):581-608, 2001. [doi]

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architectureGirish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm. cases 2001: 116-125 [doi]

2000

1999

Cameron: High level Language Compilation for Reconfigurable SystemsJeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper, J. Ross Beveridge. IEEEpact 1999: 236-244 [doi]

Combining Adaptive and Deterministic Routing: Evaluation of a Hybrid RouterDianne R. Kumar, Walid A. Najjar. canpc 1999: 150-164

Advances in the dataflow computational modelWalid A. Najjar, Edward A. Lee, Guang R. Gao. pc, 25(13-14):1907-1929, 1999.

1997

Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area RoutersDianne Miller, Walid A. Najjar. IEEEpact 1997: 64 [doi]

Preliminary Evaluation of a Hybrid Deterministic/Adaptive RouterDianne Miller, Walid A. Najjar. pcrcw 1998: 89-102 [doi]

1996

Analysis of Buffer Design for Adaptive Routing in Direct NetworksAnnette Lagman, Walid A. Najjar. mascots 1996: 134-139

Generation, Optimization, and Evaluation of Multithreaded CodeLucas Roh, Walid A. Najjar, Bhanu Shankar, A. P. Wim Böhm. jpdc, 32(2):188-204, 1996.

1995

Exploiting Data Structure Locality in the Dataflow ModelWilliam Marcus Miller, Walid A. Najjar, A. P. Wim Böhm. jpdc, 27(2):183-200, 1995.

Design of storage hierarchy in multithreaded architecturesLucas Roh, Walid A. Najjar. euromicro 1995: 271-278 [doi]

1994

1993

1992

An Analysis of Loop Latency in Dataflow ExecutionWalid A. Najjar, William Marcus Miller, A. P. Wim Böhm. isca 1992: 352-360

1991

A Quantitative Analysis of Locality in Dataflow ProgramsWilliam Marcus Miller, Walid A. Najjar, A. P. Wim Böhm. micro 1991: 12-18 [doi]

1990

Network Resilience: A Measure of Network Fault ToleranceWalid A. Najjar, Jean-Luc Gaudiot. TC, 39(2):174-181, 1990.

A data-driven execution paradigm for distributed fault-toleranceWalid A. Najjar, Jean-Luc Gaudiot. sigopsE 1990: [doi]

1989

A Single-Assignment Language in a Distributed Memory MultiprocessorParaskevas Evripidou, Walid A. Najjar, Jean-Luc Gaudiot. parle 1989: 304-320

Limits on Scalability in Gracefully Degradable Large-Scale SystemsWalid A. Najjar, Jean-Luc Gaudiot. srds 1989: 148-157

1988

Network Disconnection in Distributed SystemsWalid A. Najjar, Jean-Luc Gaudiot. icdcs 1988: 554-561

1987

Multi-Level Execution In Data-Flow ArchitecturesWalid A. Najjar, Jean-Luc Gaudiot. icpp 1987: 32-39

Reliability and Performance Modelling of Hypercube-Based MutliprocessorsWalid A. Najjar, Jean-Luc Gaudiot. mcpr 1988: 305-320