Wang Jiang Chau - researchr alias

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Viewing Publication 1 - 51 from 51

2019

Exploring Tabu search based algorithms for mapping and placement in NoC-based reconfigurable systemsGuilherme Apolinario Silva Novaes, Luiz Carlos Moreira, Wang Jiang Chau. sbcci 2019: 6 [doi]

Mapping and Placement in NoC-based Reconfigurable Systems Using an Adaptive Tabu Search AlgorithmGuilherme Apolinario Silva Novaes, Luiz Carlos Moreira, Wang Jiang Chau. lascas 2019: 145-148 [doi]

2018

On TLM traffic accuracy: A multifractal perspectiveJose Eduardo Chiarelli Bueno Filho, Wang Jiang Chau. lascas 2018: 1-4 [doi]

The functional verification of a satellite transponderVinicius Martins, Jerson Paulo Guex, Luciana Shiroma Montali, Wang Jiang Chau. lascas 2018: 1-4 [doi]

2017

Multifractal on-chip traffic generation under TLMJose Eduardo Chiarelli Bueno Filho, Wang Jiang Chau. socc 2017: 68-73 [doi]

Mixed signal verification to avoid integration mismatch in complex SoCsVinicius Martins, Wang Jiang Chau, Jerson Paulo Guex. latw 2017: 1-6 [doi]

2016

Scenario-Aware Workload Characterization Based on a Max-Plus Linear RepresentationGustavo Patino Alvarez, Wang Jiang Chau. formats 2016: 177-194 [doi]

Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulationJose Eduardo Chiarelli Bueno Filho, Jorge Luis Gonzalez Reano, Wang Jiang Chau. socc 2016: 41-46 [doi]

2015

DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation CostErnesto Villegas Castillo, Gabriele Miorandi, Davide Bertozzi, Wang Jiang Chau. arc 2015: 419-426 [doi]

Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation costErnesto Villegas Castillo, Wang Jiang Chau, Gabriele Miorandi, Davide Bertozzi. lascas 2015: 1-4 [doi]

Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable SystemsJonas Gomes Filho, Marius Strum, Wang Jiang Chau. ijrc, 2015, 2015. [doi]

Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLSRaul Acosta Hernandez, Marius Strum, Wang Jiang Chau. latw 2015: 1-6 [doi]

A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification ModelsCarlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau. et, 31(3):255-273, 2015. [doi]

2014

DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithmErnesto Villegas Castillo, Gabriele Miorandi, Wang Jiang Chau. nocs 2014: 190-191 [doi]

A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designsCarlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau. latw 2014: 1-6 [doi]

2013

Exploring the problems of placement and mapping in NoC-based reconfizurable systemsJonas Gomes Filho, Wang Jiang Chau. reconfig 2013: 1-4 [doi]

A strategy for mapping reconfigurable cores in NoCsJonas Gomes Filho, Marius Strum, Wang Jiang Chau. lascas 2013: 1-4 [doi]

Long range dependence in intrachip transaction level trafficJorge González, Gustavo Patino Alvarez, Marius Strum, Wang Jiang Chau. lascas 2013: 1-4 [doi]

Formal equivalence checking between high-level and RTL hardware designsCarlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau. latw 2013: 1-6 [doi]

Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptionsCarlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau. idt 2013: 1-6 [doi]

PrOCov: Probabilistic output coverage modelJoel Ivan Munoz Quispe, Marius Strum, Wang Jiang Chau. latw 2013: 1-6 [doi]

Manipulation of Training Sets for Improving Data Mining Coverage-Driven VerificationEdgar Leonardo Romero, Marius Strum, Wang Jiang Chau. et, 29(2):223-236, 2013. [doi]

3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mappingMartha Johanna Sepúlveda, Guy Gogniat, Daniel Mauricio Sepúlveda, Ricardo Pires, Wang Jiang Chau, Marius Strum. gecco 2013: 167-168 [doi]

QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCsJohanna Sepúlveda, Guy Gogniat, Ricardo Pires, César Pedraza, Wang Jiang Chau, Marius Strum. lascas 2013: 1-4 [doi]

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protectionJohanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum. sbcci 2013: 1-6 [doi]

An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCsJohanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum. sbcci 2013: 1-6 [doi]

2012

2011

2010

2009

The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM trainingRaul Acosta Hernandez, Marius Strum, Wang Jiang Chau, Jose Artur Quilici Gonzalez. ijcnn 2009: 1221-1228 [doi]

A PD-based methodology to enhance efficiency in testbenches with random stimulationCarlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau. sbcci 2009: [doi]

2007

A System-level Performance Evaluation Methodology for Netwrok Processors Based on Network Calculus Analytical ModelingFrederico De Faria, Marius Strum, Wang Jiang Chau. isvlsi 2007: 265-272 [doi]

2005

Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllersDuarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau. sbcci 2005: 56-61 [doi]

A Dynamically Reconfigurable Bluetooth Base Band UnitJohn Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Wang Jiang Chau. fpl 2005: 148-152

Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptorEdgar L. Romero, Marius Strum, Wang Jiang Chau. codes 2005: 327-332 [doi]

2002

BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional UnitsWang Jiang Chau, Jose Artur Quilici González, Marius Strum, Ricardo Pires. latw 2002: 64-69

A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST ApplicationsWang Jiang Chau, Paulo Sérgio Cardoso, Marius Strum, Ricardo Pires. latw 2002: 61-63

2001

Synthesis of Multi-Burst Controllers as Modified Huffman MachinesDuarte Lopes de Oliveira, Wagner Chiepa Cunha, Marius Strum, Wang Jiang Chau. sbcci 2001: 220-225 [doi]

2000

Synthesis of High Performance Extended Burst Mode Asynchronous State MachinesDuarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, Wagner Chiepa Cunha. sbcci 2000: 41-46 [doi]

Self Test Built-in Plan for Data-Path Functional UnitsJose Artur Quilici González, José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau. latw 2012: 9-14

1999

Architectural Transformations for Hierarchical Algorithmic DescriptionsMarcio Yukio Teruya, Marius Strum, Wang Jiang Chau. ifip10-5 2000: 473-484

1998

A Methodology for Minimum Area Cellular Automata GenerationPaulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Wang Jiang Chau. ats 1998: 33 [doi]

Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-CaseJosé Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau. sbcci 1998: 244-248 [doi]

1995

Collective Test Generation and Test Set CompactionWang Jiang Chau, Edward P. Stabler. iscas 1995: 2008-2011

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2019

2018

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2012

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2010

2009

2007

2005

2002

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1999

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1995

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