Xianlong Hong - researchr alias

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2011

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICsKan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong. aspdac 2011: 261-266 [doi]

2010

PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimizationLi Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong. aspdac 2010: 769-774 [doi]

Simultaneous slack budgeting and retiming for synchronous circuits optimizationShenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang. aspdac 2010: 49-54 [doi]

Effective congestion reduction for IC package substrate routingShenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong. todaes, 15(3), 2010. [doi]

Thermal Impacts of Leakage Power in 2D/3D floorplanningYuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong. jcsc, 19(7):1483-1495, 2010. [doi]

ECP- and CMP-Aware Detailed Routing Algorithm for DFMYin Shen, Qiang Zhou, Yici Cai, Xianlong Hong. tvlsi, 18(1):153-157, 2010. [doi]

An Effective Gated Clock Tree Design Based on Activity and Register Aware PlacementWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu. tvlsi, 18(12):1639-1648, 2010. [doi]

Efficient Power Network Analysis with Modeling of Inductive EffectsShan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng. ieicet, 93-A(6):1196-1203, 2010. [doi]

2009

Cell shifting aware of wirelength and overlapLiu Dawei, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong. isqed 2009: 506-510 [doi]

Buffer Planning for 3D ICsSheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto. iscas 2009: 1735-1738 [doi]

Simultaneous buffer and interlayer via planning for 3D floorplanningXu He, Sheqin Dong, Yuchun Ma, Xianlong Hong. isqed 2009: 740-745 [doi]

Integrated interlayer via planning and pin assignment for 3D ICsXu He, Sheqin Dong, Xianlong Hong, Satoshi Goto. slip 2009: 99-104 [doi]

Modern Floorplanning with Boundary Clustering ConstraintLi Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong. isvlsi 2009: 79-84 [doi]

A novel thermal optimization flow using incremental floorplanning for 3D ICsXin Li, Yuchun Ma, Xianlong Hong. aspdac 2009: 347-352 [doi]

Diffusion-driven congestion reduction for substrate topological routingShenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong. ispd 2009: 175-180 [doi]

Substrate Topological Routing for High-Density PackagesShenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong. tcad, 28(2):207-216, 2009. [doi]

Incremental power optimization for multiple supply voltage designYuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong. isqed 2009: 280-286 [doi]

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP FormulationYuchun Ma, Xin Li, Yu Wang 0002, Xianlong Hong. ieicet, 92-A(12):2979-2989, 2009. [doi]

Multi-objective Floorplanning Based on Fuzzy LogicFubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang 0002. fskd 2009: 331-335 [doi]

Statistical modeling and analysis of chip-level leakage power by spectral stochastic methodRuijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. aspdac 2009: 161-166 [doi]

A single layer zero skew clock routing in X architectureWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu. chinaf, 52(8):1466-1475, 2009. [doi]

An efficient decoupling capacitance optimization using piecewise polynomial modelsXiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles. date 2009: 1190-1195 [doi]

Thermal aware placement in 3D ICs using quadratic uniformity modeling approachHaixia Yan, Qiang Zhou, Xianlong Hong. integration, 42(2):175-180, 2009. [doi]

Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid StructuresShan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng. ieicet, 92-A(6):1476-1484, 2009. [doi]

Efficient power network analysis with complete inductive modelingShan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng. isqed 2009: 770-775 [doi]

An MTCMOS technology for low-power physical designQiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong. integration, 42(3):340-345, 2009. [doi]

2008

Application of optical proximity correction technologyYici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang. chinaf, 51(2):213-224, 2008. [doi]

Large scale P/G grid transient simulation using hierarchical relaxed approachYici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan. integration, 41(1):153-160, 2008. [doi]

Fashion: A Fast and Accurate Solution to Global Routing ProblemZhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng 0002, Lei He, Xianlong Hong. tcad, 27(4):726-737, 2008. [doi]

Logic and Layout Aware Level Converter Optimization for Multiple Supply VoltageLiangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong. ieicet, 91-A(8):2084-2090, 2008. [doi]

A novel performance driven power gating based on distributed sleep transistor networkLiangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong. glvlsi 2008: 255-260 [doi]

Full-chip routing system for reducing Cu CMP & ECP variationYanming Jia, Yici Cai, Xianlong Hong. sbcci 2008: 10-15 [doi]

Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation ModelYanming Jia, Yici Cai, Xianlong Hong. ieicet, 91-A(12):3783-3792, 2008. [doi]

A full-scale solution to the rectilinear obstacle-avoiding Steiner problemTom Tong Jing, Yu Hu, Zhe Feng 0002, Xianlong Hong, Xiaodong Hu, Guiying Yan. integration, 41(3):413-425, 2008. [doi]

Vertical via design techniques for multi-layered P/G networksShuai Li, Jin Shi, Yici Cai, Xianlong Hong. aspdac 2008: 623-628 [doi]

LP based white space redistribution for thermal via planning and performance optimization in 3D ICsXin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong. aspdac 2008: 209-212 [doi]

Topological routing to maximize routability for package substrateShenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong. dac 2008: 566-569 [doi]

Symmetry constraint based on mismatch analysis for analog layout in SOI technologyJiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto. aspdac 2008: 772-775 [doi]

Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace MethodNing Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. tcad, 27(11):1996-2006, 2008. [doi]

IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power OptimizationXiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong. isqed 2008: 873-876 [doi]

Gate planning during placement for gated clock networkWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu. iccd 2008: 128-133 [doi]

Low Power Gated Clock Tree Driven PlacementWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu. ieicet, 91-A(2):595-603, 2008. [doi]

Leakage power optimization for clock network using dual-Vth technologyWeixiang Shen, Yici Cai, Xianlong Hong. iscas 2008: 2769-2772 [doi]

Activity and register placement aware gated clock network designWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu. ispd 2008: 182-189 [doi]

DFM Based Detailed Routing Algorithm for ECP and CMPYin Shen, Yici Cai, Qiang Zhou, Xianlong Hong. isqed 2008: 357-360 [doi]

Zero skew clock routing in X-architecture based on an improved greedy matching algorithmWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu. integration, 41(3):426-438, 2008. [doi]

Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and FloorplanXiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong. ieicet, 91-A(12):3443-3450, 2008. [doi]

A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage VariationYibo Wang, Yici Cai, Xianlong Hong. isvlsi 2008: 221-226 [doi]

Low power clock buffer planning methodology in F-D placement for large scale circuit designYanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian. aspdac 2008: 370-375 [doi]

Heuristic power/ground network and floorplan co-design methodXiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong. aspdac 2008: 617-622 [doi]

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimationXing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong. fpl 2008: 559-562 [doi]

Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement AlgorithmHaixia Yan, Qiang Zhou, Xianlong Hong. isqed 2008: 289-292 [doi]

2007

Congestion Driven Buffer Planning for X-ArchitectureHongjie Bai, Sheqin Dong, Xianlong Hong. isqed 2007: 835-840 [doi]

Power Delivery Aware Floorplanning for Voltage Island DesignsYici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong. isqed 2007: 350-355 [doi]

Voltage Island Generation in Cell Based Dual-Vdd DesignYici Cai, Bin Liu, Qiang Zhou, Xianlong Hong. ieicet, 90-A(1):267-273, 2007. [doi]

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing AlgorithmZhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong. aspdac 2007: 256-261 [doi]

Statistical model order reduction for interconnect circuits considering spatial correlationsJeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. date 2007: 1508-1513 [doi]

Partitioning-based decoupling capacitor budgeting via sequence of linear programmingJeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. integration, 40(4):516-524, 2007. [doi]

Logic and Layout Aware Voltage Island Generation for Low Power DesignLiangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong. aspdac 2007: 666-671 [doi]

An effective buffer planning algorithm for IP based fixed-outline SOC placementOu He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong. glvlsi 2007: 564-569 [doi]

Dummy fill aware buffer insertion during routingYanming Jia, Yici Cai, Xianlong Hong. glvlsi 2007: 31-36 [doi]

lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) ComplexityTom Tong Jing, Zhe Feng 0002, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan. tcad, 26(11):2073-2079, 2007. [doi]

Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk ApproachLe Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan. aspdac 2007: 751-756 [doi]

Efficient Thermal via Planning Approach and Its Application in 3-D FloorplanningZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng. tcad, 26(4):645-658, 2007. [doi]

Thermal-driven Symmetry Constraint for Analog Layout with CBL RepresentationJiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong. aspdac 2007: 191-196 [doi]

An efficient quadratic placement based on search space traversing technologyYongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu. integration, 40(3):253-260, 2007. [doi]

Micro-architecture Pipelining Optimization with Throughput-Aware FloorplanningYuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou. aspdac 2007: 920-925 [doi]

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networksNing Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong. iccad 2007: 48-53 [doi]

Activity-Aware Registers Placement for Low Power Gated Clock Tree ConstructionWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu. isvlsi 2007: 383-388 [doi]

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-ArchitectureWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu. isqed 2007: 299-304 [doi]

Pattern-Based Iterative Method for Extreme Large Power/Ground AnalysisJin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong. tcad, 26(4):680-692, 2007. [doi]

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power ConsiderationYibo Wang, Yici Cai, Xianlong Hong, Yi Zou. ieicet, 90-A(5):1028-1037, 2007. [doi]

Clock-Tree Aware Placement Based on Dynamic Clock-Tree BuildingYanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai. iscas 2007: 2040-2043 [doi]

Effective Acceleration of Iterative Slack Distribution ProcessXinjie Wei, Yici Cai, Xianlong Hong. iscas 2007: 1077-1080 [doi]

APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placementYaoguang Wei, Sheqin Dong, Xianlong Hong. integration, 40(4):406-419, 2007. [doi]

Physical aware clock skew reschedulingXinjie Wei, Yici Cai, Xianlong Hong. glvlsi 2007: 473-476 [doi]

An accurate and efficient probabilistic congestion estimation model in x architectureYaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma. slip 2007: 25-32 [doi]

Unified Quadratic Programming Approach For 3-D Mixed Mode PlacementHaixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou. iscas 2007: 3411-3414 [doi]

Interconnect Power Optimization Based on Timing AnalysisLiu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong. isvlsi 2007: 119-124 [doi]

CMP-aware Maze Routing Algorithm for Yield EnhancementHailong Yao, Yici Cai, Xianlong Hong. isvlsi 2007: 239-244 [doi]

A Fast 3D-BSG Algorithm for 3D Packing ProblemLingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma. iscas 2007: 2044-2047 [doi]

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuitsPingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou. iccad 2007: 590-597 [doi]

A Yield-Driven Gridless RouterQiang Zhou, Yici Cai, Duo Li, Xianlong Hong. jcst, 22(5):653-660, 2007. [doi]

New timing and routability driven placement algorithms for FPGA synthesisYue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong. glvlsi 2007: 570-575 [doi]

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial ChaosYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang. aspdac 2007: 367-372 [doi]

2006

An ::::O::::(::::n::::log::::n::::) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry planeZhe Feng 0002, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan. ispd 2006: 48-55 [doi]

Floorplanning for 2.5-D system integration using multi-layer-BSG structureSheqin Dong, Shuyi Zheng, Xianlong Hong. iscas 2006: [doi]

A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF PrincipleSheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong. jcis 2006: [doi]

Localized On-Chip Power Delivery Network Optimization via Sequence of Linear ProgrammingJeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. isqed 2006: 272-277 [doi]

DFM-aware Routing for Yield EnhancementXianlong Hong, Yici Cai, Hailong Yao, Duo Li. apccas 2006: 1091-1094 [doi]

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integrationZhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani. todaes, 11(2):325-345, 2006. [doi]

Integrating dynamic thermal via planning with 3D floorplanning algorithmZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng. ispd 2006: 178-185 [doi]

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designsBin Liu, Yici Cai, Qiang Zhou, Xianlong Hong. aspdac 2006: 582-587 [doi]

Signal-path driven partition and placement for analog circuitDi Long, Xianlong Hong, Sheqin Dong. aspdac 2006: 694-699 [doi]

A novel technique integrating buffer insertion into timing driven placementLijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang. iscas 2006: [doi]

General Floorplans with L/T-Shaped Blocks Using Corner Block ListYuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu. jcst, 21(6):922-926, 2006. [doi]

Efficient early stage resonance estimation techniques for C4 packageJin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong. aspdac 2006: 826-831 [doi]

Performance and power aware buffered tree constructionYibo Wang, Yici Cai, Xianlong Hong. iscas 2006: [doi]

Clock Skew Scheduling Under Process VariationsXinjie Wei, Yici Cai, Xianlong Hong. isqed 2006: 237-242 [doi]

Efficient process-hotspot detection using range pattern matchingHailong Yao, Subarna Sinha, Charles Chiang, Xianlong Hong, Yici Cai. iccad 2006: 625-632 [doi]

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