Yean-Kuen Fang - researchr alias

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Viewing Publication 1 - 7 from 7

2014

Effect of gate barrier and channel buffer layer on electric properties and transparence of the a-IGZO thin film transistorCheng-I. Lin, Yean-Kuen Fang, Wei-Chao Chang, Mao-Wei Chiou, Chih-Wei Chen. mr, 54(5):905-910, 2014. [doi]

2012

x/n-LTPS/glass thin film MOS Schottky diode CO gas sensing performances on operating temperatureFeng-Renn Juang, Yean-Kuen Fang, Hung-Yu Chiu. mr, 52(2):425-429, 2012. [doi]

A novel method to improve cell endurance window in source-side injection split gate flash memoryYong-Shiuan Tsair, Yean-Kuen Fang, Feng-Renn Juang, Yu-Hsiung Wang, Wen-Ting Chu, Yung-Tao Lin, Luan Tran. mr, 52(6):1055-1059, 2012. [doi]

2010

Improvement of TDDB reliability, characteristics of HfO::2:: high-k/metal gate MOSFET device with oxygen post deposition annealingChia-Wei Hsu, Yean-Kuen Fang, Wen-Kuan Yeh, Chun-Yu Chen, Yen-Ting Chiang, Feng-Renn Juang, Chien Ting Lin, Chieh-Ming Lai. mr, 50(5):618-621, 2010. [doi]

2008

Significantly improving sub-90 nm CMOSFET performances with notch-gate enhanced high tensile-stress contact etch stop layerChia-Wei Hsu, Yean-Kuen Fang, Wen-Kuan Yeh, Chien Ting Lin. mr, 48(11-12):1791-1794, 2008. [doi]

2007

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETsChieh-Ming Lai, Yean-Kuen Fang, Chien Ting Lin, Chia-Wei Hsu, Wen-Kuan Yeh. mr, 47(6):944-952, 2007. [doi]

2002

High voltage tolerant ESD design for analog applications in deep submicron CMOS technologiesChung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, Shen Tu, Mark K. L. Chen, Mi-Chang Chang. cicc 2002: 89-92 [doi]

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