Yi-Yu Liu - researchr alias

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Viewing Publication 1 - 22 from 22

2023

Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph MonomorphismYi-Sian Ciou, An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu. tcad, 42(11):4329-4333, November 2023. [doi]

ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package DesignJun-Sheng Wu, Chi-an Pan, Yi-Yu Liu. todaes, 28(5), September 2023. [doi]

2021

TSE: Two-Step Elimination for MLC STT-RAM Last-Level CacheJen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang. TC, 70(9):1498-1510, 2021. [doi]

2020

Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process**This work was partially supported by Synopsys, TSMC, and MOST of Taiwan under Grant No's MOST 109-2636-E-011-002An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu. iccad 2020: 1-6 [doi]

2017

A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability EnhancementsYen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang. tvlsi, 25(3):820-832, 2017. [doi]

2016

A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancementsYen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang. date 2016: 79-84 [doi]

2014

Hybrid LUT and SOP Reconfigurable ArchitecturePo-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu. jise, 30(1):65-84, 2014. [doi]

Buffer Design and Assignment for Structured ASICPo-Yang Hsu, Yi-Yu Liu. jise, 30(1):107-124, 2014. [doi]

2013

Dual-addressing memory architecture for two-dimensional memory access patternsYen-Hao Chen, Yi-Yu Liu. date 2013: 71-76 [doi]

Memory management for dual-addressing memory architectureTing-Wei Hung, Yen-Hao Chen, Yi-Yu Liu. ieiceee, 10(15):20130467, 2013. [doi]

Routability optimization for crossbar-switch structured ASIC designMei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu. todaes, 18(3):39, 2013. [doi]

2010

Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design StyleFu-Wei Chen, Yi-Yu Liu. tcad, 29(12):2046-2050, 2010. [doi]

Identifying Prostate Cancer-Related Networks from Microarray Data Based on Genotype-Phenotype Networks Using Markov Blanket SearchHsiang-Yuan Yeh, Yi-Yu Liu, Cheng-Yu Yeh, Von-Wun Soo. bibe 2010: 302-303 [doi]

2009

Performance-driven dual-rail insertion for chip-level pre-fabricated designFu-Wei Chen, Yi-Yu Liu. date 2009: 308-311 [doi]

Buffer design and optimization for lut-based structured ASIC design stylesPo-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu. glvlsi 2009: 377-380 [doi]

2008

Wire Sizing Alternative - An Uniform Dual-rail Routing ArchitectureFu-Wei Chen, Yi-Yu Liu. date 2008: 796-799 [doi]

2007

Crosstalk-Aware Domino-Logic SynthesisYi-Yu Liu, TingTing Hwang. tcad, 26(6):1155-1161, 2007. [doi]

2006

Crosstalk-aware domino logic synthesisYi-Yu Liu, TingTing Hwang. date 2006: 1312-1317 [doi]

Crosstalk minimization in logic synthesis for PLAsYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang. todaes, 11(4):890-915, 2006. [doi]

2004

Crosstalk Minimization in Logic Synthesis for PLAYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang. date 2004: 790-795 [doi]

2001

A construction of minimal delay Steiner tree using two-pole delay modelLiYi Lin, Yi-Yu Liu, TingTing Hwang. aspdac 2001: 126-132 [doi]

Binary decision diagram with minimum expected path lengthYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu. date 2001: 708-712 [doi]

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