Yuejian Wu - researchr alias

researchr

You are not signed in
Sign in
Sign up

2011

Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC DesignsYuejian Wu, Sandy Thomson, Dale Mutcher, Eric Hall. tvlsi, 19(4):629-637, 2011. [doi]

2008

Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASICYuejian Wu, Sandy Thomson, Han Sun, Chandra Bontu, Eric Hall. socc 2008: 55-58 [doi]

2006

Low Power SoC Memory BISTYuejian Wu, André Ivanov. dft 2006: 197-205 [doi]

Fast detection of data retention faults and other SRAM cell open defectsJosh Yang, Baosheng Wang, Yuejian Wu, André Ivanov. tcad, 25(1):167-180, 2006. [doi]

2005

2004

Designs for Reducing Test Time of Distributed Small Embedded SRAMsBaosheng Wang, Yuejian Wu, André Ivanov. dft 2004: 120-128 [doi]

Low power decoding of BCH codesYuejian Wu. iscas 2004: 369-372

2003

Testing ASICs with multiple identical coresYuejian Wu, Paul N. MacDonald. tcad, 22(3):327-336, 2003. [doi]

2002

Design and Test of a 9-port SRAM for a 100Gb/s STS-1 SwitchRobert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu. mtdt 2002: 83 [doi]

2001

Shadow write and read for at-speed BIST of TDM SRAMsYuejian Wu, Liviu Calin. itc 2001: 985-994

1999

Interconnect delay fault testing with IEEE 1149.1Yuejian Wu, Paul Soong. itc 1999: 449-457

Scan-based BIST fault diagnosisYuejian Wu, Saman Adham. tcad, 18(2):203-211, 1999. [doi]

1998

Diagnosis of Scan Chain FailuresYuejian Wu. dft 1998: 217 [doi]

1997

Built-In Self-Test for Multi-Port RAMsYuejian Wu, Sanjay Gupta. ats 1997: 398-403 [doi]

1996

BIST Fault Diagnosis in Scan-Based VLSI EnvironmentsYuejian Wu, Saman Adham. itc 1996: 48-57

1995

Reducing Hardware with Fuzzy Multiple Signature AnalysisYuejian Wu, André Ivanov. dt, 12(1):68-74, 1995. [doi]

Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BISTYuejian Wu, André Ivanov. TC, 44(6):817-825, 1995.