Yukio Mitsuyama - researchr alias

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2010

A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior ModelingTakehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. wisa 2011: 107-121 [doi]

Adaptive performance control with embedded timing error predictive sensors for subthreshold circuitsHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. aspdac 2010: 361-362 [doi]

Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold CircuitsHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. tvlsi, 18(7):1118-1129, 2010. [doi]

Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolutionRyo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. isqed 2010: 839-844 [doi]

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay ResolutionRyo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. ieicet, 93-A(12):2417-2423, 2010. [doi]

Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability considerationHiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. isqed 2010: 646-651 [doi]

2009

Coarse-grained dynamically reconfigurable architecture with flexible reliabilityDawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye. fpl 2009: 186-192 [doi]

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error PredictionHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. ieicet, 92-A(12):3094-3102, 2009. [doi]

Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error predictionHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. aspdac 2009: 266-271 [doi]

Tuning-friendly body bias clustering for compensating random variability in subthreshold circuitsKoichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. islped 2009: 51-56 [doi]

An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed ControllabilityKoichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. ieicet, 92-C(2):281-285, 2009. [doi]

2008

2005

Architecture of IEEE802.11i Cipher Algorithms for Embedded SystemsYukio Mitsuyama, Motoki Kimura, Takao Onoye, Isao Shirakawa. ieicet, 88-A(4):899-906, 2005. [doi]

2001

VLSI architecture of dynamically reconfigurable hardware-based cipherYukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa. iscas 2001: 734-737 [doi]

A dynamically reconfigurable hardware-based cipher chipYukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa. aspdac 2001: 11-12 [doi]

1999

FeRAM Circuit Technology for System on a ChipKoji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Y. Meng. eh 1999: 193 [doi]