Zhanping Chen - researchr alias

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Viewing Publication 1 - 26 from 26

2022

A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic TechnologyStafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni. vlsit 2022: 136-137 [doi]

2017

2 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field ProgrammingZhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya. jssc, 52(4):933-939, 2017. [doi]

2016

A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOSSarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, M. Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang. jssc, 51(4):1003-1008, 2016. [doi]

2010

1T1R Bit Cell in 32 nm High-k Metal-Gate CMOSSarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, M. Brian Pedersen, Kevin Zhang. jssc, 45(4):863-868, 2010. [doi]

2009

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS TechnologyFatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr. jssc, 44(1):148-154, 2009. [doi]

2008

2006

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supplyKevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr. jssc, 41(1):146-151, 2006. [doi]

2005

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reductionKevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr. jssc, 40(4):895-901, 2005. [doi]

2002

2001

On effective I::DDQ:: testing of low-voltage CMOS circuits using leakage control techniquesZhanping Chen, Liqiong Wei, Kaushik Roy. tvlsi, 9(5):718-725, 2001. [doi]

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessorsJames Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De. islped 2001: 147-152 [doi]

2000

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control TechniquesZhanping Chen, Liqiong Wei, Kaushik Roy. isqed 2000: 181-188 [doi]

Estimation of power dissipation using a novel power macromodelingtechniqueZhanping Chen, Kaushik Roy, Edwin K. P. Chong. tcad, 19(11):1363-1369, 2000. [doi]

1999

1998

A Power Macromodeling Technique Based on Power SensitivityZhanping Chen, Kaushik Roy. dac 1998: 678-683 [doi]

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacksZhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy. islped 1998: 239-244 [doi]

Efficient statistical approach to estimate power considering uncertain properties of primary inputsZhanping Chen, Kaushik Roy, Tan-Li Chou. tvlsi, 6(3):484-492, 1998. [doi]

Estimation of power sensitivity in sequential circuits with power macromodeling applicationZhanping Chen, Kaushik Roy, Edwin K. P. Chong. iccad 1998: 468-472 [doi]

Estimation of average switching power under accurate modeling of signal correlationsZhanping Chen, Kaushik Roy 0001, Yibin Ye. cicc 1998: 507-510 [doi]

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS CircuitsLiqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De. dac 1998: 489-494 [doi]

1997

Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputsZhanping Chen, Kaushik Roy, Tan-Li Chou. iccad 1997: 40-44 [doi]

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