Zvonko G. Vranesic - researchr alias

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Viewing Publication 1 - 77 from 77

2013

Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAsFranjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown. trets, 6(4):16, 2013. [doi]

2009

Enhancements to FPGA design methodology using streamingFranjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown. fpl 2009: 294-301 [doi]

2008

Towards Compilation of Streaming Programs into FPGA HardwareFranjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown. fdl 2008: 67-72 [doi]

Stream Programming for FPGAsFranjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown. fdl 2009: 241-253 [doi]

2007

On Digital Search Trees - A Simple Method for Constructing Balanced Binary TreesFranjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown. ICSOFT 2007: 61-68

2006

A Multithreaded Soft Processor for SoPC Area ReductionBlair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown. fccm 2006: 131-142 [doi]

Adaptive FPGAs: High-Level Architecture and a Synthesis MethodValavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic. fpl 2006: 1-8 [doi]

Heuristics for Area Minimization in LUT-Based FPGA Technology MappingValavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic. tcad, 25(11):2331-2340, 2006. [doi]

2005

Experiences with Soft-Core Processor DesignFranjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown. ipps 2005: [doi]

2003

A fast algorithm for OR-AND-OR synthesisDebatosh Debnath, Zvonko G. Vranesic. tcad, 22(9):1166-1176, 2003. [doi]

Use of HDLs in teaching of computer hardware coursesZvonko G. Vranesic, Stephen Dean Brown. wcae 2003: 16 [doi]

2002

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic DevicesValavan Manohararajah, Terry Borer, Stephen Dean Brown, Zvonko G. Vranesic. fpl 2002: 232-241 [doi]

A Deterministic Multivariate Interpolation Algorithm for Small Finite FieldsZeljko Zilic, Zvonko G. Vranesic. TC, 51(9):1100-1105, 2002. [doi]

2001

Structural analysis and generation of synthetic digital circuits with memorySteven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic. tvlsi, 9(1):223-226, 2001. [doi]

2000

1999

The Multicluster Architecture: Reducing Processor Cycle Time Through PartitioningKeith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic. ijpp, 27(5):327-356, 1999.

The memory/logic interface in FPGAs with large embedded memory arraysSteven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic. tvlsi, 7(1):80-91, 1999. [doi]

1998

1997

1996

1995

1994

On Scheduling in Multiprocessor Systems Using Fuzzy LogicAlireza Kaviani, Zvonko G. Vranesic. ismvl 1994: 141-147

Performance Prediction for Different Consistency Schemes in Distributed Shared Memory SystemsSinisa Srbljic, Zvonko G. Vranesic, Leo Budin. hpdc 1994: 295-302

1993

A stochastic model to predict the routability of field-programmable gate arraysStephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic. tcad, 12(12):1827-1838, 1993. [doi]

Physically Based Modeling and Control of TurningMichiel van de Panne, Eugene Fiume, Zvonko G. Vranesic. cvgip, 55(6):507-521, 1993.

Architectural Support for Block Transfers in a Shared-Memory MultiprocessorSteven J. E. Wilton, Zvonko G. Vranesic. spdp 1993: 51-55

Current-Mode CMOS Galois Field CircuitsZeljko Zilic, Zvonko G. Vranesic. ismvl 1993: 245-250

1992

A detailed router for field-programmable gate arraysStephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic. tcad, 11(5):620-628, 1992. [doi]

Cache Consistency in Hierarchical-Ring-Based MultiprocessorsKeith I. Farkas, Zvonko G. Vranesic, Michael Stumm. sc 1992: 348-357

Towards the Realization of 4-Valued CMOS CircuitsKonrad Lei, Zvonko G. Vranesic. ismvl 1992: 104-110

1991

1990

1988

Parallel standard cell placement algorithms with quality equivalent to simulated annealingJonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic. tcad, 7(3):387-396, 1988. [doi]

1986

Synthesis of Multivalued Multithreshold Functions for CCD ImplementationMostafa H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic. TC, 35(2):124-133, 1986.

Implementation of a Dynamic Address Assignment Protocol in a Local Area NetworkWayne M. Loucks, William I. Kwak, Zvonko G. Vranesic. cn, 11:133-146, 1986.

1985

FERMTOR: A Tunable Multiprocessor ArchitectureJonathan Rose, Wayne M. Loucks, Zvonko G. Vranesic. micro, 5(4):5-17, 1985. [doi]

1984

Comments on Fault Diagnosis of MOS Combinational Networks Kuang-Wei Chiang, Zvonko G. Vranesic. TC, 33(10):947, 1984.

1983

A Tree Representation of Combinational NetworksKuang-Wei Chiang, Zvonko G. Vranesic. TC, 32(3):315-319, 1983.

On fault detection in CMOS logic networksKuang-Wei Chiang, Zvonko G. Vranesic. dac 1983: 50-56 [doi]

A Pipelined Distributed Arithmetic PFFT ProcessorPaul Chow, Zvonko G. Vranesic, Jui Lin Yen. TC, 32(12):1128-1136, 1983.

1981

Key compression using segment stringsC. L. Lam, Zvonko G. Vranesic. is, 6(2):139-146, 1981.

TORNET: A local area networkZvonko G. Vranesic, V. Carl Hamacher, Wayne M. Loucks, Safwat G. Zaky. sigcomm 1981: 180-187 [doi]

1980

Ternary Rate-MultipliersH. T. Mouftah, K. C. Smith, Zvonko G. Vranesic. TC, 29(10):929-931, 1980.

Teaching Computer StructuresZvonko G. Vranesic, Kenneth J. Thurber, Sperry Univac. Computer, 13(6):19-25, 1980. [doi]

1978

A. Higher Radix Technique for Fault Detection in Many-Valued Multithreshold NetworksA. Druzeta, Zvonko G. Vranesic. TC, 27(11):1070-1073, 1978.

Review of Content addressable parallel processors by Caxton C. Foster. Van Nostrand Reinhold Co. 1976Zvonko G. Vranesic. sigarch, 7(1):24, 1978. [doi]

1977

Multiple-Valued Logic: An Introduction and OverviewZvonko G. Vranesic. TC, 26(12):1181-1182, 1977.

1974

Application of Multithreshold Elements in the Realization of Many-Valued Logic NetworksA. Druzeta, Zvonko G. Vranesic, A. S. Sedra. TC, 23(11):1194-1198, 1974. [doi]

Fault Detection of Binary Sequential Machines Using R-Valued Test MachinesDonald A. Sheppard, Zvonko G. Vranesic. TC, 23(4):352-358, 1974. [doi]

Engineering aspects of multi-valued logic systemsZvonko G. Vranesic, Kenneth C. Smith. Computer, 7(9):34-41, 1974. [doi]

1973

Design of a Fully Variable - Length Structured MinicomputerZvonko G. Vranesic, V. Carl Hamacher, Y. Y. Leung. isca 1973: 251-255

1972

Ternary logic in parallel multipliersZvonko G. Vranesic, V. Carl Hamacher. cj, 15(3):254-258, 1972. [doi]

Functional Transformation in Simplification of Multivalued Switching FunctionsZvonko G. Vranesic, K. M. Waliuzzaman. TC, 21(1):102-105, 1972. [doi]

1970

A Many-Valued Algebra for Switching SystemsZvonko G. Vranesic, E. Stewart Lee, Kenneth C. Smith. TC, 19(10):964-971, 1970. [doi]

On Decomposition of Multi-Valued Switching FunctionsK. M. Waliuzzaman, Zvonko G. Vranesic. cj, 13(4):359-362, 1970.

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