- B. A. Al Jassani, N. Urquhart, A. E. A. Almaini. State assignment for sequential circuits using multi-objective genetic algorithm. IET Computers & Digital Techniques, 5(4):296-305, 2011.
- Miguel Morales-Sandoval, Claudia Feregrino Uribe, P. Kitsos. Bit-serial and digit-serial GF(2:::m:::)Montgomery multipliers using linear feedback shift registers. IET Computers & Digital Techniques, 5(2):86-94, 2011.
- Ken S. Stevens, Alexandre Yakovlev. Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems. IET Computers & Digital Techniques, 5(4):316-317, 2011.
- Yuan Xie, Pol Marchal. Editorial- three-dimensional integrated circuits design. IET Computers & Digital Techniques, 5(3):159, 2011.
- Mario R. Casu. Half-buffer retiming and token cages for synchronous elastic circuits. IET Computers & Digital Techniques, 5(4):318-330, 2011.
- George Rosario Jagadeesh, Thambipillai Srikanthan, C. M. Lim. Field programmable gate array-based acceleration of shortest-path computation. IET Computers & Digital Techniques, 5(4):231-237, 2011.
- Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar. Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Computers & Digital Techniques, 5(3):205-212, 2011.
- Basel Halak, Alexandre Yakovlev. Statistical analysis of crosstalk-induced errors for on-chip interconnects. IET Computers & Digital Techniques, 5(2):104-112, 2011.
- Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta. Near-optimal Y-routed delay trees in nanometric interconnect design. IET Computers & Digital Techniques, 5(1):36-48, 2011.
- Benjamin Carrión Schäfer, Kazutoshi Wakabayashi. Precision tunable RTL macro-modelling cycle-accurate power estimation. IET Computers & Digital Techniques, 5(2):95-103, 2011.