- Shamik Das, Garrett S. Rose. Introduction to Special Issue: Highlights of NANOARCH 09. JETC, 7(1):1, 2011.
- Sezer Gören, H. Fatih Ugurdag, Okan Palaz. Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort. JETC, 7(3):12, 2011.
- Aleksandr Biberman, Kyle Preston, Gilbert Hendry, Nicolás Sherwood-Droz, Johnnie Chan, Jacob S. Levy, Michal Lipson, Keren Bergman. Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors. JETC, 7(2):7, 2011.
- Raymond G. Beausoleil. Large-scale integrated photonics for high-performance interconnects. JETC, 7(2):6, 2011.
- Zheng Li, Moustafa Mohamed, Xi Chen, Hongyu Zhou, Alan Rolf Mickelson, Li Shang, Manish Vachharajani. Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication. JETC, 7(2):8, 2011.
- Aaron Dingler, Michael T. Niemier, Xiaobo Sharon Hu, Evan Lent. Performance and Energy Impact of Locally Controlled NML Circuits. JETC, 7(1):2, 2011.
- Li Shang, Qianfan Xu. Introduction to nanophotonic communication technology integration. JETC, 7(2):5, 2011.
- Mark J. Cianchetti, David H. Albonesi. A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors. JETC, 7(2):9, 2011.
- Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O Connor, Junchen Liu, Maimouna Amadou, Gabriela Nicolescu. Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method. JETC, 7(1):3, 2011.
- Meng Zhang, Niraj K. Jha. FinFET-Based Power Management for Improved DPA Resistance with Low Overhead. JETC, 7(3):10, 2011.