IEEE Trans. on CAD of Integrated Circuits and Systems - researchr journal

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Dariusz Czysz, Grzegorz Mrugalski, Neelanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(1):117-126, 2010.
Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang. A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(2):240-245, 2010.
Yifang Liu, Jiang Hu. A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(2):223-234, 2010.
Wen-Wen Hsieh, S. L. Chen, I-Sheng Lin, TingTing Hwang. A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(2):289-298, 2010.
Chen-Ling Chou, Radu Marculescu. Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(1):78-91, 2010.
Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue. Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(2):250-260, 2010.
Quang Dinh, Deming Chen, Martin D. F. Wong. A Routing Approach to Reduce Glitches in Low Power FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(2):235-240, 2010.
S. Das, B. K. Sikdar. A Scalable Test Structure for Multicore Chip. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(1):127-137, 2010.
Nick Soveiko, Michel S. Nakhla, Ramachandra Achar. Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(1):65-77, 2010.
L.-T. Wang, X. Wen, S. Wu, H. Furukawa, H.-J. Chao, B. Sheu, J. Guo, W.-B. Jone. Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(2):299-312, 2010.