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- Yifang Liu, Rupesh S. Shelar, Jiang Hu. Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(3):416-426, 2011.
- Jason Cong, Bin Liu 0006, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang. High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(4):473-491, 2011.
- M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli. An Efficient Gate Library for Ambipolar CNTFET Logic. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(2):242-255, 2011.
- Seungwhun Paik, Seonggwan Lee, Youngsoo Shin. Retiming Pulsed-Latch Circuits With Regulating Pulse Width. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(8):1114-1127, 2011.
- Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth. GRIP: Global Routing via Integer Programming. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(1):72-84, 2011.
- Vittorio Rizzoli, Diego Masotti, Franco Mastri, E. Montanari. System-Oriented Harmonic-Balance Algorithms for Circuit-Level Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(2):256-269, 2011.
- Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay. Floorplanning for Partially Reconfigurable FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(1):8-17, 2011.
- Luca Benini, Luca P. Carloni. Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2010. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(4):492-493, 2011.
- Sachin S. Sapatnekar. Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(1):1, 2011.