- Tarik Saidani, Lionel Lacassagne, Joel Falcou, Claude Tadonki, Samir Bouaziz. Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector. T. HiPEAC, 3:177-200, 2011.
- Matthias A. Blumrich, Valentina Salapura, Alan Gara. Exploring the Architecture of a Stream Register-Based Snoop Filter. T. HiPEAC, 3:93-114, 2011.
- M. M. Waliullah. Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems. T. HiPEAC, 3:256-274, 2011.
- Maziar Goudarzi, Tohru Ishihara, Hamid Noori. Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies. T. HiPEAC, 3:275-299, 2011.
- Harald Devos, Jan Van Campenhout, Ingrid Verbauwhede, Dirk Stroobandt. Constructing Application-Specific Memory Hierarchies on FPGAs. T. HiPEAC, 3:201-216, 2011.
- Miquel Moretó, Francisco J. Cazorla, Alex RamÃrez, Mateo Valero. Dynamic Cache Partitioning Based on the MLP of Cache Misses. T. HiPEAC, 3:3-23, 2011.
- Subhradyuti Sarkar, Dean M. Tullsen. Data Layout for Cache Performance on a Multithreaded Architecture. T. HiPEAC, 3:43-68, 2011.
- Jan Hoogerbrugge, Andrei Terechko. A Multithreaded Multicore System for Embedded Media Processing. T. HiPEAC, 3:154-173, 2011.
- Tobias Klug, Michael Ott, Josef Weidendorfer, Carsten Trinitis. autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems. T. HiPEAC, 3:219-235, 2011.
- Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous. Improving Branch Prediction by Considering Affectors and Affectees Correlations. T. HiPEAC, 3:69-88, 2011.