Abstract is missing.
- Signal Processing for ControlWilliam S. Levine. 3-22 [doi]
- Digital Signal Processing in Home EntertainmentKonstantinos Konstantinides. 23-41 [doi]
- MPEG Reconfigurable Video CodingMarco Mattavelli, Jörn W. Janneck, Mickaël Raulet. 43-67 [doi]
- Signal Processing for High-Speed LinksNaresh Shanbhag, Andrew C. Singer, Hyeon-Min Bae. 69-101 [doi]
- Video CompressionYu-Han Chen, Liang-Gee Chen. 103-121 [doi]
- Low-power Wireless Sensor Network PlatformsJukka Suhonen, Mikko Kohvakka, Ville Kaseva, Timo D. Hämäläinen, Marko Hännikäinen. 123-160 [doi]
- Signal Processing for Cryptography and Security ApplicationsMiroslav Knezevic, Lejla Batina, Elke De Mulder, Junfeng Fan, Benedikt Gierlichs, Yong Ki Lee, Roel Maes, Ingrid Verbauwhede. 161-177 [doi]
- High-Energy PhysicsAnthony E. Gregerson, Michael J. Schulte, Katherine Compton. 179-211 [doi]
- Medical Image ProcessingRaj Shekhar, Vivek Walimbe, William Plishker. 213-242 [doi]
- Signal Processing for Audio HCIDmitry N. Zotkin, Ramani Duraiswami. 243-265 [doi]
- Distributed Smart Cameras and Distributed Computer VisionMarilyn Wolf, Jason Schlessman. 267-280 [doi]
- ArithmeticOscar Gustafsson, Lars Wanhammar. 283-327 [doi]
- Application-Specific Accelerators for CommunicationsYang Sun, Kiarash Amiri, Michael Brogioli, Joseph R. Cavallaro. 329-362 [doi]
- FPGA-based DSPJohn McAllister. 363-392 [doi]
- General-Purpose DSP ProcessorsJarmo Takala. 393-413 [doi]
- Application Specific Instruction Set DSP ProcessorsDake Liu. 415-447 [doi]
- Coarse-Grained Reconfigurable Array ArchitecturesBjorn De Sutter, Praveen Raghavan, Andy Lambrechts. 449-484 [doi]
- Multi-core Systems on ChipLuigi Carro, Mateus Beck Rutzig. 485-514 [doi]
- DSP Systems using Three-Dimensional (3D) Integration TechnologyTong Zhang 0002, Yangyang Pan, Yiran Li. 515-541 [doi]
- Mixed Signal TechniquesOlli Vainio. 543-571 [doi]
- C Compilers and Code Optimization for DSPsBjörn Franke. 575-601 [doi]
- Compiling for VLIW DSPsChristoph W. Kessler. 603-638 [doi]
- Software Compilation Techniques for MPSoCsRainer Leupers, Weihua Sheng, Jerónimo Castrillón. 639-678 [doi]
- DSP Instruction Set SimulationFlorian Brandner, R. Nigel Horspool, Andreas Krall. 679-705 [doi]
- Optimization of Number RepresentationsWonyong Sung. 707-738 [doi]
- Intermediate Representations for Simulation and ImplementationJerker Bengtsson. 739-767 [doi]
- Embedded C for Digital Signal ProcessingBryan E. Olivier. 769-787 [doi]
- Signal Flow Graphs and Data Flow GraphsKeshab K. Parhi, Yanni Chen. 791-816 [doi]
- Systolic ArraysYu Hen Hu, Sun-Yuan Kung. 817-849 [doi]
- Decidable Signal Processing Dataflow Graphs: Synchronous and Cyclo-Static Dataflow GraphsSoonhoi Ha, Hyunok Oh. 851-874 [doi]
- Mapping Decidable Signal Processing Graphs into FPGA ImplementationsRoger Woods. 875-898 [doi]
- Dynamic and Multidimensional Dataflow GraphsShuvra S. Bhattacharyya, Ed F. Deprettere, Joachim Keinert. 899-930 [doi]
- Polyhedral Process NetworksSven Verdoolaege. 931-965 [doi]
- Kahn Process Networks and a Reactive ExtensionMarc Geilen, Twan Basten. 967-1006 [doi]
- Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-ChipIuliana Bacivarov, Wolfgang Haid, Kai Huang 0001, Lothar Thiele. 1007-1040 [doi]
- Integrated Modeling using Finite State Machines and Dataflow GraphsJoachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Christian Zebelein. 1041-1075 [doi]