Randal E. Bryant, Miroslav N. Velev. Verification of Pipelined Microprocessors by Comparing Memory Execution Sequences in Symbolic Simulation. In R. K. Shyamasundar, Kazunori Ueda, editors, Advances in Computing Science - ASIAN 97, Third Asian Computing Science Conference, Kathmandu, Nepal, December 9-11, 1997, Proceedings. Volume 1345 of Lecture Notes in Computer Science, pages 18-31, Springer, 1997.
Abstract is missing.