Timing-constrained I/O buffer placement for flip-chip designs

Zhi-Wei Chen, Jin-Tai Yan. Timing-constrained I/O buffer placement for flip-chip designs. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011. pages 619-624, IEEE, 2011. [doi]

Abstract

Abstract is missing.