MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit

C. B. Hsu, Y. S. Hong, J. B. Kuo. MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit. In 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014. pages 60-63, IEEE, 2014. [doi]

Abstract

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