Table of Contents

• Adaptive Locks: Combining Transactions and Locks for Efficient ConcurrencyTakayuki Usui, Reimer Behrends, Jacob Evans, Yannis Smaragdakis. 3-14 [doi]
• Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative MultithreadingCarlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González. 15-25 [doi]
• Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip MultiprocessorsAbhishek Bhattacharjee, Margaret Martonosi. 29-40 [doi]
• Interprocedural Load Elimination for Dynamic Optimization of Parallel ProgramsRajkishore Barik, Vivek Sarkar. 41-52 [doi]
• Quantifying the Potential of Program Analysis PeripheralsMohit Tiwari, Shashidhar Mysore, Timothy Sherwood. 53-63 [doi]
• Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL ProcessorTarik Saidani, Joel Falcou, Claude Tadonki, Lionel Lacassagne, Daniel Etiemble. 67-76 [doi]
• A Task-Centric Memory Model for Scalable Accelerator ArchitecturesJohn H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel. 77-87 [doi]
• SHIP: Scalable Hierarchical Power Control for Large-Scale Data CentersXiaorui Wang, Ming Chen, Charles Lefurgy, Tom W. Keller. 91-100 [doi]
• Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory ArchitecturesWangyuan Zhang, Tao Li. 101-112 [doi]
• Core-Selectability in Chip MultiprocessorsHashem Hashemi Najaf-abadi, Niket Kumar Choudhary, Eric Rotenberg. 113-122 [doi]
• Chainsaw: Using Binary Matching for Relative Instruction Mix ComparisonTipp Moseley, Dirk Grunwald, Ramesh Peri. 125-135 [doi]
• tm_db: A Generic Debugging Library for Transactional ProgramsMaurice Herlihy, Yossi Lev. 136-145 [doi]
• StealthTest: Low Overhead Online Software Testing Using Transactional MemoryJayaram Bobba, Weiwei Xiong, Luke Yen, Mark D. Hill, David A. Wood. 146-155 [doi]
• CPROB: Checkpoint Processing with Opportunistic Minimal RecoveryAndrew D. Hilton, Neeraj Eswaran, Amir Roth. 159-168 [doi]
• Architecture Support for Improving Bulk Memory Copying and Initialization PerformanceXiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar Iyer. 169-180 [doi]
• Oblivious Routing in On-Chip Bandwidth-Adaptive NetworksMyong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel A. Kinsy, Tina Wen, Srinivas Devadas. 181-190 [doi]
• Exploiting Parallelism with Dependence-Aware SchedulingXiaotong Zhuang, Alexandre E. Eichenberger, Yangchun Luo, Kevin O Brien, Kathryn M. O Brien. 193-202 [doi]
• ITCA: Inter-task Conflict-Aware CPU Accounting for CMPsCarlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero. 203-213 [doi]
• Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous ArchitecturesAmir Hormati, Yoonseo Choi, Manjunath Kudlur, Rodric M. Rabbah, Trevor N. Mudge, Scott A. Mahlke. 214-223 [doi]
• DDCache: Decoupled and Delegable Cache Data and MetadataHemayet Hossain, Sandhya Dwarkadas, Michael C. Huang. 227-236 [doi]
• Zero-Value Caches: Cancelling Loads that Return ZeroMd. Mafijul Islam, Per Stenström. 237-245 [doi]
• Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level PartitioningQingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, Xiaodong Zhang, P. Sadayappan. 246-257 [doi]
• Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor SystemDaniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller. 261-270 [doi]
• Automatic Tuning of Discrete Fourier Transforms Driven by Analytical ModelingBasilio B. Fraguela, Yevgen Voronenko, Markus Püschel. 271-280 [doi]
• Analytical Modeling of Pipeline ParallelismAngeles G. Navarro, Rafael Asenjo, Siham Tabik, Calin Cascaval. 281-290 [doi]
• FASTM: A Log-based Hardware Transactional Memory with Fast Abort RecoveryMarc Lupon, Grigorios Magklis, Antonio González. 293-302 [doi]
• Improving Signatures by Locality Exploitation for Transactional MemoryRicardo Quislant, Eladio Gutiérrez, Oscar G. Plata, Emilio L. Zapata. 303-312 [doi]
• Mapping Out a Path from Hardware Transactional Memory to Speculative MultithreadingLeo Porter, Bumyong Choi, Dean M. Tullsen. 313-324 [doi]
• Polyhedral-Model Guided Loop-Nest Auto-VectorizationKonrad Trifunovic, Dorit Nuzman, Albert Cohen, Ayal Zaks, Ira Rosen. 327-337 [doi]
• Region Based Structure Layout Optimization by Selective Data CopyingSandya S. Mannarswamy, Ramaswamy Govindarajan, Rishi Surendran. 338-347 [doi]
• Data Layout Transformation for Enhancing Data Locality on NUCA Chip MultiprocessorsQingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, Tin-Fook Ngai. 348-357 [doi]
• SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip MultiprocessorsLei Jin, Sangyeun Cho. 361-371 [doi]
• Using Aggressor Thread Information to Improve Shared Cache Management for CMPsWanli Liu, Donald Yeung. 372-383 [doi]
• Cache Sharing Management for Performance Fairness in Chip MultiprocessorsXing Zhou, Wenguang Chen, Weimin Zheng. 384-393 [doi]