Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH

Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi. Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. In 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada. pages 334-339, IEEE Computer Society, 2004. [doi]

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