A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache - researchr publication

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Kyungsu Kang, Sangho Park, Jong-Bae Lee, Luca Benini, Giovanni De Micheli. A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache. In Luca Fanucci, Jürgen Teich, editors, 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016. pages 1465-1468, IEEE, 2016. [doi]

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