Integrating Logic Analyzer Functionality into VHDL Designs

Günter Knittel, Stefanie Mayer, Christian Rothländer. Integrating Logic Analyzer Functionality into VHDL Designs. In ReConFig 08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings. pages 127-132, IEEE Computer Society, 2008. [doi]

Abstract

Abstract is missing.