High speed low complexity FPGA-based FIR filters using pipelined adder graphs

Martin Kumm, Peter Zipf. High speed low complexity FPGA-based FIR filters using pipelined adder graphs. In Russell Tessier, editor, 2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, December 12-14, 2011. pages 1-4, IEEE, 2011. [doi]

Abstract

Abstract is missing.