Low temperature multi-layer wafer level package for chip scale atomic clock (CSAC)

Nannan Li, Yangxi Zhang, Ningli Zhu, Yunhui Zhu, Chengchen Gao, Jing Chen. Low temperature multi-layer wafer level package for chip scale atomic clock (CSAC). In 10th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, NEMS 2015, Xi'an, China, April 7-11, 2015. pages 481-484, IEEE, 2015. [doi]

Abstract

Abstract is missing.