Probabilistic maximum error modeling for unreliable logic circuits

Karthikeyan Lingasubramanian, Sanjukta Bhanja. Probabilistic maximum error modeling for unreliable logic circuits. In Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud, editors, Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007. pages 223-226, ACM, 2007. [doi]

Abstract

Abstract is missing.