Automated constraint-driven topology synthesis for analog circuits

Oliver Mitea, Markus Meissner, Lars Hedrich, P. Jores. Automated constraint-driven topology synthesis for analog circuits. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011. pages 1662-1665, IEEE, 2011. [doi]

Abstract

Abstract is missing.