A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

Kelageri Nagaraj, Sandip Kundu. A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009. pages 292-295, IEEE, 2009. [doi]

Abstract

Abstract is missing.