Correctly rounded floating-point division for DSP-enabled FPGAs

Bogdan Pasca. Correctly rounded floating-point division for DSP-enabled FPGAs. In Dirk Koch, Satnam Singh, Jim Tørresen, editors, 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012. pages 249-254, IEEE, 2012. [doi]

Abstract

Abstract is missing.