Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar. Reducing the signal Electromigration effects on different logic gates by cell layout optimization. In IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015. pages 1-4, IEEE, 2015. [doi]
Abstract is missing.