Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula. Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. In 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India. pages 243-248, IEEE Computer Society, 2003. [doi]
Abstract is missing.