Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface

Jan Schat. Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface. In 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006. pages 878-881, IEEE, 2006. [doi]

Abstract

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