Hiran Tennakoon, Carl Sechen. Efficient and accurate gate sizing with piecewise convex delay models. In William H. Joyner Jr., Grant Martin, Andrew B. Kahng, editors, Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005. pages 807-812, ACM, 2005. [doi]
Abstract is missing.