Delay modeling of CMOS/CPL logic circuits

Yuanzhong Wan, Maitham Shams. Delay modeling of CMOS/CPL logic circuits. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 5613-5616, IEEE, 2005. [doi]

Abstract

Abstract is missing.