A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations

Mingyu Wang, Fang Wang, Shaojun Wei, Zhaolin Li. A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations. Microelectronics Journal, 47:19-30, 2016. [doi]

Abstract

Abstract is missing.