Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler. Designing a RISC CPU in Reversible Logic. In Jaakko Astola, Radomir S. Stankovic, editors, 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011, Tuusula, Finland, May 23-25, 2011. pages 170-175, IEEE, 2011. [doi]
Abstract is missing.