An architecture-level cache simulation framework supporting advanced PMA STT-MRAM

Bi-Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao. An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. In Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015. pages 7-12, IEEE, 2015. [doi]

Abstract

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