Abstract is missing.
- Combining Structural and Symbolic Methods for the Verification of Concurrent SystemsJordi Cortadella. 2-7 [doi]
- Logic and Functional Verification in a Commercial Semiconductor EnvironmentJainendra Kumar, Carl Pixley. 8-15 [doi]
- How to Make Concurrent Programs Highly Reliable- More than State Space AnalysisNaoshi Uchihira. 16-23 [doi]
- System-Level Design Models and Implementation TechniquesLuciano Lavagno. 24 [doi]
- Hierarchical Concurrent Finite State Machines in PtolemyBilung Lee, Edward A. Lee. 34-40 [doi]
- Visual Formalisms RevisitedRadu Grosu, Gheorghe Stefanescu, Manfred Broy. 41-51 [doi]
- A Translation of Statecharts into Signal Approach of Time, InteroperabilityJean-René Beauvais, Roland Houdebine, Paul Le Guernic, Éric Rutten, Thierry Gautier. 52 [doi]
- Verification of Parameterized Asynchronous Circuits: A Case StudyTomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera. 64-74 [doi]
- Unbounded Verification Results by Finite-State Compositional Techniques: 10:::any::: States and BeyondAntti Valmari, Ilkka Kokkarinen. 75 [doi]
- Modeling and Verification of Biphase Mark Protocolsin Duration Calculus Using PVSDang Van Hung. 88-98 [doi]
- Formal Verification of Real-Time Software by Symbolic Model-CheckerKazuhiro Nakamura, Satoshi Yamane. 99-108 [doi]
- Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent SystemsAntonio Cerone, David A. Kearney, George J. Milne. 109-119 [doi]
- Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL EnvironmentMichael V. Goncharov, Alexander B. Smirnov, Nikolai Starodoubtsev, Ilya V. Klotchkov. 120 [doi]
- Efficient Approach to Symbolic State Exploration of Complex Parallel ControllersKrzysztof Bilinski, Erik L. Dagless. 132-142 [doi]
- Calculating Place Capacity for Petri Nets Using UnfoldingsToshiyuki Miyamoto, Sadatoshi Kumagai. 143-151 [doi]
- Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net UnfoldingsAlex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev. 152 [doi]
- Using Object-Oriented Algebraic Nets for the Reverse Engineering of Java Programs: A Case StudyGiovanna Di Marzo Serugendo, Nicolas Guelfi. 166-176 [doi]
- Proving Correctness of Distributed Algorithms Using High-Level Petri Nets - A Case StudyJörg Desel, Ekkart Kindler. 177-186 [doi]
- Verifying Fault Tolerance of Distributed Algorithms Formally - An ExampleHagen Völzer. 187 [doi]
- Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary SimulationMiroslav N. Velev, Randal E. Bryant. 200-212 [doi]
- Event-Driven Verification of Switch-Level Correctness ConcernsRadu Negulescu. 213 [doi]
- A True Concurrency Semantics for ET-LOTOSHoward Bowman, Joost-Pieter Katoen. 228-238 [doi]
- Recursive Nets in the Box AlgebraRaymond R. Devillers, Maciej Koutny. 239-249 [doi]
- A Presentation of Regular Languages in the Assumption - Commitment FrameworkSwarup Mohalik, Ramaswamy Ramanujam. 250 [doi]
- Modeling and Analyzing Interorganizational WorkflowsWil M. P. van der Aalst. 262-272 [doi]
- A Java-based Formal Development Environment for Factory Communication SystemsClaudio Demartini, Riccardo Sisto. 273-281 [doi]
- Traffic Lights - An AutoFocus Case StudyFranz Huber, Sascha Molterer, Bernhard Schätz, Oscar Slotosch, Alexander Vilbig. 282 [doi]