Abstract is missing.
- Keynote address II: Adaptive distributed systems for space exploration: Present and futureMarco Quadrelli. [doi]
- PrefaceKhaled Benkrid, Didier Keymeulen, David Merodio, Michael Newell, Rainer Wansch, Umeshkumar D. Patel, Ahmet T. Erdogan, Niels Hadaschik, Luca Sterpone, Jelle Poupaert, Massimo Violante. [doi]
- Keynote address I: The Space reference scenario: From the present solutions to the future challenges for Thales Alenia SpaceAndrea Martelli. [doi]
- Worst case error rate predictions and mitigation schemes for Virtex-4 FPGAs on solar orbiterHolger Michel, Frank Bubenhagen, Kai Grurmann, Tobias Lange, Björn Fiethe, Harald Michalik. 1-8 [doi]
- On the optimal reconfiguration times for TMR circuits on SRAM based FPGAsLuca Sterpone, Anees Ullah. 9-14 [doi]
- Adaptive FDIR framework for payload data processing systems using reconfigurable FPGAsFelix Siegle, Tanya Vladimirova, Omar Emam, Jørgen Ilstad. 15-22 [doi]
- On self-adaptive resource allocation through reinforcement learningJacopo Panerati, Filippo Sironi, Matteo Carminati, Martina Maggio, Giovanni Beltrame, Piotr J. Gmytrasiewicz, Donatella Sciuto, Marco D. Santambrogio. 23-30 [doi]
- Evolutionary algorithms that use runtime migration of detector processes to reduce latency in event-based systemsChristoffer Loffler, Christopher Mutschler, Michael Philippsen. 31-38 [doi]
- Hardware-based parallel firefly algorithm for embedded applicationsDaniel M. Muñoz, Carlos H. Llanos, Leandro dos Santos Coelho, Mauricio Ayala-Rincón. 39-46 [doi]
- Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systemsFabrizio Ferrandi, Pier Luca Lanzi, Christian Pilato, Donatella Sciuto, Antonino Tumeo. 47-54 [doi]
- Implementation of an initial-configuration based on self-reconfiguration for an on-board processorFlorian Rittner, Robért Glein. 55-62 [doi]
- Reconfigurable platforms for Data Processing on scientific space instrumentsFrank Bubenhagen, Björn Fiethe, Tobias Lange, Harald Michalik, Holger Michel. 63-70 [doi]
- A framework to model self-adaptive Computing SystemsCristiana Bolchini, Matteo Carminati, Antonio Miele, Elisa Quintarelli. 71-78 [doi]
- A systematic generation of optimized heterogeneous 3D Networks-on-Chip architectureMichael Opoku Agyeman, Ali Ahmadinia. 79-83 [doi]
- Runtime adaptation on dataflow HPC platformsRiccardo Cattaneo, Christian Pilato, Matteo Mastinu, Oliver Kadlcek, Oliver Pell, Marco Domenico Santambrogio. 84-91 [doi]
- Self-adaptation techniques for mixed-signal SiGe BiCMOS ICsVladimir Bratov, Vladimir Katzman, Aleksandr Gryunshpan, Andrey Bratov. 92-98 [doi]
- AIDI: An adaptive image denoising FPGA-based IP-core for real-time applicationsStefano Di Carlo, Paolo Prinetto, Daniele Rolfo, Pascal Trotta. 99-106 [doi]
- FPGA implementation of a lossy compression algorithm for hyperspectral images with a high-level synthesis toolLucana Santos, Jose Fco. Lopez, Roberto Sarmiento, Raffaele Vitulli. 107-114 [doi]
- Parallelised fault-tolerant Integer KLT implementation for lossless hyperspectral image compression on board satellitesNor Rizuan Mat Noor, Tanya Vladimirova. 115-122 [doi]
- Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processorsJulien Heulot, Jani Boutellier, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi. 123-129 [doi]
- Combined HW-SW adaptive clone-resistant functions as physical security anchorsMarc Fyrbiak, Christan Kison, Marc Jeske, Wael Adi. 130-137 [doi]
- Hardware requirements of communication-centric machine learning algorithmsLauri Koskinen, Enrico Roverato. 138-143 [doi]
- Hardware realization of GALS based cortical column systemsAnita Tino, Gul N. Khan, Fei Yuan. 144-149 [doi]
- Suppression of constant modulus interference in multimode transceivers using an adaptive nonlinear circuitHooman Habibi, Erwin J. G. Janssen, Yan Wu 0001, Dusan M. Milosevic, Jan W. M. Bergmans, Peter G. M. Baltus. 150-155 [doi]
- Methodology and reconfigurable architecture for effective placement of variable-size hardware tasksNicolas Marques, Hassan Rabah, Slavisa Jovanovic, Eric Dabellani, Serge Weber. 156-163 [doi]
- Image filter evolution on the Xilinx Zynq PlatformRoland Dobai, Lukás Sekanina. 164-171 [doi]
- Four-configuration-context optically reconfigurable gate array with a MEMS interleaving methodYuichiro Yamaji, Minoru Watanabe. 172-177 [doi]
- Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAsAli Ebrahim, Khaled Benkrid, Xabier Iturbe, Chuan Hong. 178-183 [doi]
- Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architectureLuca Sterpone, Davide Sabena, Anees Ullah, Mario Porrmann, Jens Hagemeyer, Jørgen Ilstad. 184-188 [doi]
- Heterogeneous hardware accelerators interconnect: An overviewCuong Pham-Quoc, Zaid Al-Ars, Koen Bertels. 189-197 [doi]
- A2B: An integrated framework for designing heterogeneous and reconfigurable systemsChristian Pilato, Riccardo Cattaneo, Gianluca Durelli, Alessandro Antonio Nacci, Marco Domenico Santambrogio, Donatella Sciuto. 198-205 [doi]
- Non volatile memory for FPGA booting in spaceAnna Arbat, Cristiano Calligaro, Vladislav Dayan, Evgeny Pikhay, Yakov Roizin. 204-208 [doi]
- Formal approaches to SEU testing in FPGAsCinzia Bernardeschi, Luca Cassano, Andrea Domenici. 209-216 [doi]