Abstract is missing.
- Ruler: high-speed packet matching and rewriting on NPUsTomas Hruby, Kees van Reeuwijk, Herbert Bos. 1-10 [doi]
- Optimization of pattern matching algorithm for memory based architectureCheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang. 11-16 [doi]
- Towards high-performance flow-level packet processing on multi-core network processorsYaxuan Qi, Bo Xu, Fei He, Baohua Yang, Jianming Yu, Jun Li. 17-26 [doi]
- Frame shared memory: line-rate networking on commodity hardwareJohn Giacomoni, John K. Bennett, Antonio Carzaniga, Douglas C. Sicker, Manish Vachharajani, Alexander L. Wolf. 27-36 [doi]
- Experimental evaluation of a coarse-grained switch schedulerCharlie Wiseman, Jonathan S. Turner, Ken Wong, Brandon Heller. 37-38 [doi]
- Design of a network architecture with inherent data path securityTilman Wolf. 39-40 [doi]
- Experimenting with buffer sizes in routersNeda Beheshti, Jad Naous, Yashar Ganjali, Nick McKeown. 41-42 [doi]
- To CMP or not to CMP: analyzing packet classification on modern and traditional parallel architecturesRandy Smith, Dan Gibson, Shijin Kong. 43-44 [doi]
- Flow-slice: a novel load-balancing scheme for multi-path switching systemsLei Shi, Bin Liu, Changhua Sun, Zhengyu Yin, Laxmi N. Bhuyan, H. Jonathan Chao. 45-46 [doi]
- Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architectureAvinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri. 47-56 [doi]
- Performance scalability of a multi-core web serverBryan Veal, Annie Foong. 57-66 [doi]
- Automated task distribution in multicore network processors using statistical analysisArindam Mallik, Yu Zhang, Gokhan Memik. 67-76 [doi]
- Optimal packet scheduling in output-buffered optical switches with limited-range wavelength conversionLin Liu, Yuanyuan Yang. 77-86 [doi]
- Low-latency scheduling in large switchesWladek Olesinski, Nils Gura, Hans Eberle, Andres Mejia. 87-96 [doi]
- On LID assignment in infiniBand networksWickus Nienaber, Xin Yuan, Zhenhai Duan. 97-106 [doi]
- Frame-aggregated concurrent matching switchBill Lin, Isaac Keslassy. 107-116 [doi]
- Congestion management for non-blocking clos networksNikolaos Chrysos. 117-126 [doi]
- Compiling PCRE to FPGA for accelerating SNORT IDSAbhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan. 127-136 [doi]
- High-speed packet classification using binary search on lengthHyesook Lim, Ju-Hyoung Mun. 137-144 [doi]
- An improved algorithm to accelerate regular expression evaluationMichela Becchi, Patrick Crowley. 145-154 [doi]
- Curing regular expressions matching algorithms from insomnia, amnesia, and acalculiaSailesh Kumar, Balakrishnan Chandrasekaran, Jonathan S. Turner, George Varghese. 155-164 [doi]
- Enhancing interoperability and stateful analysis of cooperative network intrusion detection systemsMichele Colajanni, Daniele Gozzi, Mirco Marchetti. 165-174 [doi]
- High-speed detection of unsolicited bulk emailsSheng-Ya Lin, Cheng-Chung Tan, Jyh-Charn Liu, Michael Oehler. 175-184 [doi]
- A programmable message classification engine for session initiation protocol (SIP)Arup Acharya, Xiping Wang, Charles Wright. 185-194 [doi]
- DPICO: a high speed deep packet inspection engine using compact finite automataChristopher L. Hayes, Yan Luo. 195-203 [doi]