Abstract is missing.
- A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS TechnologyS. Sarkar, A. Ghosh, S. Banerjee. 1-4 [doi]
- A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCsVipul Katyal, Randall L. Geiger, Degang Chen. 5-8 [doi]
- A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCsXin Zhang, Dunshan Yu, Shimin Sheng. 9-12 [doi]
- INL Prediction Method in Pipeline ADCsGholamreza Nikandish, Behnam Sedighi, Mehrdad Sharif Bakhtiar. 13-16 [doi]
- Differential OPAMP with Inherent Common-Mode Control and Self-Biased Cascodes in 120nm CMOSFranz Schlögl, H. Dietrich, Horst Zimmermann. 17-20 [doi]
- Improving Source-Follower Buffer for High-Speed ADC TestingX. P. Fan, P. K. Chan. 21-24 [doi]
- 0.7 V Monolithic CMOS LNA for 802.11 A/B WLAN ApplicationWang-Chi Cheng, Cheong-fat Chan, Suyi Tao, King-Keung Mok. 25-28 [doi]
- A New Linearity Enhancing Technique for Low Noise AmplifiersAmit Gopal M. Purohit, Sanjeev Gupta. 29-32 [doi]
- A CMOS Current-Reused Transceiver with Stacked LNA and Mixer for WPANSang-Sun Yoo, Seok-Oh Yun, Soo-Hwan Shin, Hyung-Joun Yoo. 33-36 [doi]
- 2.4 GHz High IIP3 and Low-Noise Down-conversion MixerJun-Da Chen, Zhi-Ming Lin. 37-40 [doi]
- Compact Modeling of MOSFETs Channel Noise for Low-Noise RF ICs DesignZhi-Qiang Lu, Feng-chang Lai. 41-44 [doi]
- An 8 GHz Variable Gain Low Noise Amplifier (VGLNA) Utilizing Parallel Inter-Stage ResonanceLini Lee, S. S. Jamuar, R. M. Sidek, S. Khatun. 45-48 [doi]
- Digital Filter Design: Global Solutions via Polynomial OptimizationWu-Sheng Lu. 49-52 [doi]
- Design of Arbitrary FIR Digital Filters with Group Delay ConstraintYongzhi Liu, Zhiping Lin. 53-56 [doi]
- Symmetry Development for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay FiltersTian-Bo Deng. 57-60 [doi]
- A Methodology for Automatic Hardware Synthesis of Multiplier-less Digital Filters with Prescribed Output AccuracyS. C. Chan, K. M. Tsui, S. H. Zhao. 61-64 [doi]
- A New Method for Designing Constrained Causal Stable IIR Variable Digital FiltersS. C. Chan, K. M. Tsui, H. K. Kwan. 65-68 [doi]
- New Structures for Single Filter Based Frequency-Response Masking ApproachChun Zhu Yang, Yong Lian. 69-72 [doi]
- 3D Shape Acquisition and Arbitrary View Image Generation from Monocular Image Based on Primitive DecompositionKatsuya Kondo, A. Yamachika, Syoji Kobashi, Yutaka Hata. 73-76 [doi]
- Cauchy based Rate-Distortion Optimization Model for H.264 Rate ControlN. Eiamjumrus, Supavadee Aramvith. 77-80 [doi]
- A Fast Watermarking System for H.264/AVC VideoCong-Van Nguyen, David B. H. Tay, Guang Deng. 81-84 [doi]
- A New Efficient Approach for Removal of Impulse Noise for Color ImagesYasuhide Wakabayashi, Akira Taguchi. 85-88 [doi]
- A 0.18µm CMOS Gaussian Monocycle Pulse Circuit Design for UWBR. Hidayat, K. Dejhan, P. Moungnoul, Y. Miyanaga. 89-92 [doi]
- VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication SystemShingo Yoshizawa, Yoshikazu Miyanaga. 93-96 [doi]
- RaceCheck: A Race Logic Audit Program For SoC DesignsT. Chan. 97-100 [doi]
- A Development and Validation Platform for Communication SOC DesignYuChen Sun, ChingYao Huang. 101-104 [doi]
- A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC ApplicationsDuo Sheng, Ching-Che Chung, Chen-Yi Lee. 105-108 [doi]
- Design of Adaptive Deblocking Filter for H.264/AVC Decoder SOCYang Kun, Zhang Chun, Wang Zhihua. 109-112 [doi]
- An Adaptive Low-Power Control Scheme for On-Chip Network ApplicationsChun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen. 113-118 [doi]
- An Efficient Clocking Scheme for On-Chip CommunicationsMahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha. 119-122 [doi]
- Semi-Blind Time Domain Equalization for MIMO-OFDM SystemsShaodan Ma, Tung-Sang Ng. 123-126 [doi]
- Linear Precoding For MIMO STC-OFDM And Blind Channel EstimationYonghong Zeng, Abdul Rahim Leyman. 127-130 [doi]
- Multi-degree Random Cyclic Delay Diversity in MISO Systems with Frequency-Domain SchedulingZhengang Pan, Jingxiu Liu, Lan Chen, Kenichi Higuchi, Mamoru Sawahashi. 131-134 [doi]
- Throughput Maximization in Multiuser MIMO Downlink with Individual QoS ConstraintsGan Zheng, Kai-Kit Wong, Tung-Sang Ng. 135-138 [doi]
- Iterative Symbol-by-symbol Decision Feedback Detection for MIMO-ISI ChannelsXuan Huan Nguyen, Jinho Choi. 139-142 [doi]
- An EM-Based Joint Channel Estimation and Data Detection for SIMO SystemsThe-Hanh Pham, Arumugam Nallanathan, Ying-Chang Liang. 143-146 [doi]
- Development of a Wireless Sensor Network System for Power Constrained ApplicationsJ. Y. Khan, D. F. Hall, P. D. Turner. 147-150 [doi]
- Design of a Long-Range Wireless Sensor NodeSimon Willis, Cornelis J. Kikkert. 151-154 [doi]
- Hierarchical Decision-making of Multi-sensor System for State Estimation of Machining ProcessLiang Wei, Li Yinhua, Li Jie. 155-158 [doi]
- An Optimized Scheme of Energy Consumption in Wireless Sensor MAC ProtocolWei Jing, Xu Pingping. 159-162 [doi]
- Noise Analysis and Simulation of Chopper AmplifierTao Yin, Haigang Yang, Quan Yuan, Guoping Cui. 167-170 [doi]
- A Low-power 7-b 33-Msamples/s Switched-current Pipelined ADC for Motor ControlGuo-Ming Sung, Jyi-Hrong Tzeng, Chen-Shen Liao, Shih-Chieh Shu. 171-174 [doi]
- Low Power Current-Mode Algorithmic ADC in Half Flash (BCD)S. Chuenarom, S. Maitreechit, P. Roengruen, V. Tipsuwarnpron. 175-178 [doi]
- A Switched-Voltage High-Accuracy Sample/Hold CircuitKenji Ohno, Hiroki Matsumoto, Kenji Murao. 179-182 [doi]
- A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement TechniqueKa-Hou Ao Ieong, Seng-Pan U., Rui Paulo Martins. 183-186 [doi]
- Continuous Time Delta-Sigma Modulators with Arbitrary DAC WaveformsHossein Shamsi, Omid Shoaei. 187-190 [doi]
- A New Approach for DAC Non-linearity Compensation in Continuous Time Delta Sigma ModulatorsHossein Shamsi, Omid Shoaei. 191-194 [doi]
- Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS SystemWang-Chi Cheng, Cheong-fat Chan, Kong-Pang Pun, Oliver Chiu-sing Choy. 195-198 [doi]
- High Power CMOS Power Amplifier for WCDMAYu-Chun Huang, Zhi-Ming Lin. 199-202 [doi]
- A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning AlgorithmShuilong Huang, Zhihua Wang, Huainan Ma. 203-206 [doi]
- A CMOS Digitally Controlled RF Variable Gain AmplifierRo-Min Weng, Bing-Hung Chen. 207-209 [doi]
- A 3.125-GHz Limiting Amplifier for Optical Receiver SystemHsin-Ming Wu, Ching-Yuan Yang. 210-213 [doi]
- A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS TechnologyKo-Chi Kuo, Feng-Ji Wu. 214-217 [doi]
- Filterbank Framework for Multicarrier Systems with Improved Subcarrier SeparationYuan-Pei Lin, Chien-Chang Li, See-May Phoong. 218-221 [doi]
- Performance Analysis of the Deficient Length EDS Adaptive AlgorithmZhongkai Zhang, Tamal Bose, Li Xiao, R. Thamvichai. 222-226 [doi]
- An Alternate Approach for Developing Higher Radix FFT AlgorithmsSaad Bouguezel, M. Omair Ahmad, M. N. S. Swamy. 227-230 [doi]
- Signature Verification using Velocity-based Directional Filter BankM. Khalid Khan, M. Aurangzeb Khan, Mohammad A. U. Khan, Sungyoung Lee. 231-234 [doi]
- Multidimensional Parameters Estimation of Array Signal Based on Steering VectorWeimin Jia, Minli Yao, Jianshe Song. 235-238 [doi]
- Wavelet Packet Transform for Scalable Audio EncoderSheau-Fang Lei, Hsi-Fu Lee. 239-242 [doi]
- Design of a Low Power Architecture for CABAC Encoder in H.264Chien-Chung Kuo, Sheau-Fang Lei. 243-246 [doi]
- Frame Based Error Concealment in H.264/AVC by Refined Motion PredictionHsin-Ju Feng, Chih-Hung Kuo. 247-250 [doi]
- Matched Block Detection and Motion Vector Salvage Methods for Fast H.264/AVC Inter Mode DecisionJi-Kun Lin, Hung-Ming Wang, Jar-Ferr Yang. 251-254 [doi]
- An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video CodersHeng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang. 255-258 [doi]
- Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC DecodingYi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu. 259-262 [doi]
- Modified MMSE DMC and Edge Reserving Concealment for Improving H.264 Error ResiliencePing-Yu Chen, Pau-Choo Chung. 263-266 [doi]
- An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V SensitivityChua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu. 267-270 [doi]
- An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet TransformLeibo Liu Hongying Meng, Milin Zhang. 271-274 [doi]
- VLSI Realization of Adaptive Equalizers of SIMO FIR Second Order Volterra ChannelsK. Deergha Rao, Ch. Gangadhar. 275-278 [doi]
- Design and Implementation of a Schedulable DMAC on an AMBA-Based SOPC PlatformKuan Jen Lin, Chuang Hsiang Huang, Cheng Chia Lo. 279-282 [doi]
- Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB)Wonwoo Jang, Hyunsik Kim, Sungmok Lee, Jooyoung Ha, Bongsoon Kang. 283-286 [doi]
- Adiabatic Smart CardKing-Keung Mok, Ka-Hung Tsang, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun. 287-290 [doi]
- Space-Time Decision-Directed Equalizer for SIMO Systems based on Affine Projection AlgorithmWon-Cheol Lee, Jun Su Rark, Hyung Min Chang. 291-294 [doi]
- A Turbo-BLAST method with Non-Linear MMSE Detector for MIMO-OFDM systemsJong Yoon Hwang, Dong-Kyoon Cho, Kwang Soon Kim, Keum-Chan Whang. 295-297 [doi]
- An Effective SLM-PRSC Hybrid Scheme for OFDM PAPR Reduction Based on Repeated Utilization of Identical PRSC Sequences in Time DomainSeungwoo Han. 298-301 [doi]
- Efficient Buffer Management for Retry Mechanism in InfiniBandChungwon Park, Hee Yong Youn, Youngmin Kwon. 302-304 [doi]
- Enhanced Degree Computationless Modified Euclid s AlgorithmJang Woong Park, Jae Hyun Baek, Myung Hoon Sunwoo. 305-308 [doi]
- A VLSI Design of High Speed Bit-level Viterbi DecoderMin Woo Kim, Jun Dong Cho. 309-312 [doi]
- Global Convergence Analysis of Delayed Bidirectional Associative Memory Neural NetworksR. Samli, Sabri Arik. 313-316 [doi]
- Using ANN To Predict The Best HUB LocationA. B. Aljunaid, I. AbuElMaaly, A. Sagahyroon. 317-320 [doi]
- A Generic Architecture for Intelligent System HardwareKeerthi Laal Kala, M. B. Srinivas. 321-326 [doi]
- Recognition of Musical InstrumentsHarya Wicaksana, Septian Hartono, Foo Say Wei. 327-330 [doi]
- Pareto based Multi-objective Mapping IP Cores onto NoC ArchitecturesWenbiao Zhou, Yan Zhang, Zhigang Mao. 331-334 [doi]
- Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D SchedulesMineo Kaneko. 335-338 [doi]
- A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication SystemsYoung-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Ju Kim, Kyoung-Jun Moon, Seung-Hoon Lee, Seok-Bong Hyun, Seong-Su Park. 339-342 [doi]
- A 4-bit 1.356 Gsps ADC Using Current Processing MethodJa-Hyun Koo, Yun-Jeong Kim, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim. 343-346 [doi]
- A 6-bit 2.704Gsps DAC for DS-CDMA UWBJae-Jin Jung, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim. 347-350 [doi]
- A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D ConverterKyung-Hoon Lee, Young-Jae Cho, Hee-Cheol Choi, Yong-Hyun Park, Doo-Hwan Sa, Young-Lok Kim, Seung-Hoon Lee. 351-354 [doi]
- An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLANSeong-Min Ha, Tae-Kyu Nam, K. S. Yoon. 355-358 [doi]
- A 0.18µm CMOS Fully Differential RF Demodulator for FM-UWB Based P-PAN ReceiversTian Tong, Jian Liu, Jan H. Mikkelsen, Torben Larsen. 359-362 [doi]
- A 0.18-µm CMOS UWB Low Noise Amplifier for Full-Band (3.1-10.6GHz) ApplicationRuey-Lue Wang, Shih-Chih Chen, Hsiang-Chen Kuo, Chien-Hsuan Liu. 363-366 [doi]
- 3~5 GHz Cascoded UWB Power AmplifierRuey-Lue Wang, Yan-Kuin Su, Chien-Hsuan Liu. 367-369 [doi]
- A Fully Integrated 3 to 5 GHz CMOS Mixer with Active Balun for UWB ReceiverDe-Mao Chen, Zhi-Ming Lin. 370-373 [doi]
- A Novel FFT Processor for OFDM UWB SystemsZhongjun Wang, Lee Guek Yeo, Wenzhen Li, Yanxin Yan, Yujing Ting, Masayuki Tomisawa. 374-377 [doi]
- Design of Optimal Decimation and Interpolation Filters for Low Bit-Rate Image CodingWu-Sheng Lu, A.-M. Sevcenco. 378-381 [doi]
- Multiple Description Image Coding With Hybrid RedundancyZhiming Xu, Zhiping Lin, Anamitra Makur. 382-385 [doi]
- Image Enhancement Algorithm for Hexagonal Cellular Neural NetworksChao-Hui Huang, Chin-Teng Lin. 386-389 [doi]
- Minimization of L2-Sensitivity for 2-D Separable-Denominator State-Space Digital Filters Subject to L2-Scaling ConstraintsTakao Hinamoto, Yukihiro Shibata, Wu-Sheng Lu. 390-393 [doi]
- Design of Delta Operator Based 2-D IIR Filters Using Symmetrical DecompositionI-Hung Khoo, Hari C. Reddy, P. K. Rajan. 394-397 [doi]
- A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVCChing-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao-Chang Yang, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng. 398-401 [doi]
- Unequal-arm Adaptive Rood Pattern Search with Early Terminations For Fast Block-matching Motion Estimation on H.264Bin Li, Kai-Kuang Ma. 402-405 [doi]
- Motion Vector Estimation and Adatptive Refinement for the MPEG-4 to H.264/AVC Video TranscoderSeung-Kyun Oh, HyunWook Park. 406-409 [doi]
- Exploiting Reference Frame History in H.264/AVC Motion EstimationAnjali K. Mahajan, Sandhya Kondayya, Xiao Su. 410-413 [doi]
- Fast Motion Estimation Algorithm by Finite-State Side Match for H.264 Video Coding StandardGwo-Long Li, Mei-Juan Chen. 414-417 [doi]
- Transistor Realization of Reversible TSG Gate and Reversible Adder ArchitecturesHimanshu Thapliyal, A. Prasad Vinod. 418-421 [doi]
- Redundant Adders Consume Less EnergyKavallur Gopi Smitha, H. A. H. Fahmy, A. Prasad Vinod. 422-425 [doi]
- A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit DesignRuei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu. 426-429 [doi]
- Design of Clocked Transmission Gate Adiabatic Logic Circuit Based on the 3ECEACWang Pengjun, Yu Junjun, Xu Jian. 430-433 [doi]
- A New Class AB Current-Mode Circuit for Low-Voltage ApplicationsBehnam Sedighi, Mehrdad Sharif Bakhtiar. 434-437 [doi]
- A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation SequencesA. Blad, Håkan Johansson, Per Löwenborg. 438-441 [doi]
- A Resolution- and Rate- Scalable Image Subband Coding Scheme with Backward Coding of Wavelet TreesJiangling Guo, Sunanda Mitra, Tanja Karp, Brian Nutter. 442-445 [doi]
- Design of Time Domain Equalizers Incorporating Radio Frequency Interference SuppressionYa-Wen Wu, Yuan-Pei Lin, Chien-Chang Li, See-May Phoong. 446-449 [doi]
- Flexible Filter Bank Dimensioning for Multicarrier Modulation and Frequency Domain EqualizationAri Viholainen, Tero Ihalainen, Tobias Hidalgo Stitz, Yuan Yang, Markku Renfors. 450-453 [doi]
- Prototype Filter Design for a Cosine-Modulated Filterbank TransmultiplexerDah-Chung Chang, Da-Long Lee. 454-457 [doi]
- VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWTBasant K. Mohanty, Pramod Kumar Meher. 458-461 [doi]
- Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet TransformBasant K. Mohanty, Pramod Kumar Meher. 462-465 [doi]
- DCT Sign Only Correlation and Its Application to Image RegistrationFitri Arnia, Ikue Iizuka, Hiroyuki Kobayashi, F. Masaaki, Hitoshi Kiya. 466-469 [doi]
- Image Registration using Fractional Fourier TransformKamalesh Kumar Sharma, Shiv Dutt Joshi. 470-473 [doi]
- Design of an Area Efficient High-Speed Color FDWT ProcessorS. Raghunath, S. M. Aziz. 474-477 [doi]
- System Design of Implantable Micro-stimulator for Medical TreatmentsShou-Jung Chang, Wen-Yaw Chung, Chiung-Cheng Chuang. 478-481 [doi]
- A Wide-Range and High PSRR CMOS Voltage Reference for Implantable DeviceWen-Yaw Chung, Chiung-Cheng Chuang, Ji-Ting Chen. 482-485 [doi]
- Some Recent Developments in the Design of Biopotential Amplifiers for ENG Recording SystemsJ. Taylor, D. Masanotti, V. Seetohul, S. Hao. 486-489 [doi]
- A Micropower CMOS Amplifier for Portable Surface EMG RecordingP. K. Chan, G. A. Hanasusanto, H. B. Tan, V. K. S. Ong. 490-493 [doi]
- Low Power SAW-Based Oscillator for an Implantable Multisensor MicrosystemL.-F. Tanguay, M. Sawan. 494-497 [doi]
- A Miniaturized, Power-Efficent Stimulator Output Stage Based on the Bridge Rectifier CircuitXiao Liu, Andreas Demosthenous, Nick Donaldson. 498-501 [doi]
- A Low-Power Low-Voltage Amplifier for Heart Rate SensorGin Kooi Lim, T. Hui Teo. 502-505 [doi]
- Design of 3-4GHz Tunable Low Noise LC-QVCO for IEEE 802.11a WLAN ApplicationH. Ramiah, T. Zainal, A. Zulkifli. 506-509 [doi]
- A 6.5-GHz LC VCO with Integrated-Transformer TuningChia-Chieh Tu, Ching-Yuan Yang. 510-513 [doi]
- A CMOS Dual-Band Voltage Controlled OscillatorS.-L. Jang, Y.-H. Chuang, C. C. Chen, S.-H. Lee, J.-F. Lee. 514-517 [doi]
- A Low-Voltage 2.4GHz VCO with 3D Helical InductorsShao-Hua Lee, Yun-Hsueh Chuang, Li-Ren Chi, Sheng-Lyang Jang, Jian-Feng Lee. 518-521 [doi]
- 0.8 V GPS band CMOS VCO with 29 Tuning RangeWang-Chi Cheng, Cheong-fat Chan, Kong-Pang Pun, Oliver Chiu-sing Choy. 522-525 [doi]
- A Novel 16-bit CMOS Digitally Controlled OscillatorS. M. Rezaul Hasan. 526-529 [doi]
- A Wide Input-Range Sigma Delta Modulator for Applications to Spread-Spectrum Clock GeneratorYao-Huang Kao, Yi-Bin Hsieh. 530-533 [doi]
- Bit-Serial Digital Filter Implementation using a Custom C CompilerDan Cyca, Laurence E. Turner. 534-537 [doi]
- Towards an Efficient Simulation of Multi-Language Descriptions of Heterogeneous SystemsMathieu Dubois, El Mostapha Aboulhamid, Frédéric Rousseau. 538-541 [doi]
- FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave FiltersArjuna Madanayake, Leonard T. Bruton. 542-545 [doi]
- Broadband Beamforming of Bandpass Plane Waves using 2D FIR Trapezoidal Filters at BasebandThushara K. Gunaratne, Leonard T. Bruton. 546-549 [doi]
- Efficient Implementation of the Fast Filter Bank For Critically Decimated SystemsJun Wei Lee, Yong Ching Lim. 550-553 [doi]
- Optimized Design of Extrapolated Impulse Response FIR Filters with Raised-Cosine WindowsLihong Zhou, Wenjiang Pei, Pengcheng Xi, Zhenya He. 558-561 [doi]
- A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video EncodingYu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, Youn-Long Lin. 562-565 [doi]
- Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX ProcessorGuang-Huei Lin, Sao-Jie Chen, R. B. Lee, Yu Hen Hu. 566-569 [doi]
- Implementation of a H.264 decoder with Template-based Communication RefinementSang-yong Yoon, Sanggyu Park, Soolk Chae. 570-573 [doi]
- Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video TranscodingShen Li, Lingfeng Li, Takeshi Ikenaga, Shunichi Ishiwata, Masataka Matsui, Satoshi Goto. 574-577 [doi]
- Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVCChing-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao Li, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng. 578-581 [doi]
- An Improved Soft-Input CAVLC Decoder for Mobile Communication ApplicationsTsu-Ming Liu, Chen-Yi Lee. 582-585 [doi]
- High Performance Context Adaptive Variable Length Coding Encoder for MPEG-4 AVC/H.264 Video CodingMin-Chi Tsai, Tian-Sheuan Chang. 586-589 [doi]
- Asynchronous Design Methodology for an Efficient Implementation of Low power ALUP. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, C. R. Mandal. 590-593 [doi]
- Low Power Multiplier Designs Based on Improved Column Bypassing SchemesYin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu. 594-597 [doi]
- A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino TechniquesSteve Hung-Lung Tu, Chih-Hung Yen. 598-601 [doi]
- Low Power Multiplier with Bypassing and Tree StrucutureKo-Chi Kuo, Chi-Wen Chou. 602-605 [doi]
- Asynchronous Design of Modular Multiplication Using Adaptive Radix ComputationJun-Hong Chen, Ming-Der Shieh, Haw-Shiuan Wu, Wen-Ching Lin. 606-609 [doi]
- New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth s AlgorithmChiou-Yng Lee, Yu-Hsin Chiu, Che Wun Chiou. 610-613 [doi]
- High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving CapabilityChiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai. 614-617 [doi]
- Advances in Global Optimization: Novel Function Transformation ApproachesL. S. Zhang. 618-621 [doi]
- A Filled Function Method for Box-constrained System of Nonlinear EquationsZhi-You Wu, M. Mammadov, Fu-Sheng Bai. 622-625 [doi]
- An Optimization Problem on Two-Partition of Jobs for Profit AllocationQuanle Chen, Xiaoqiang Cai, Yanhong Gu. 626-629 [doi]
- A Recursive Digital Filter Design using Global Optimization TechniqueZhiyou Wu, Yanhong Gu. 630-633 [doi]
- Linear Incentive Contract for Principal-agent Problem with Asymmetric Information and Moral HazardLi Shanliang, Wang Chunhua. 634-637 [doi]
- Results on Exactness Properties of the HP-ALF for Inequality ConstraintsXuewu Du. 638-641 [doi]
- A Total Unimodularity Based Branch-and-Bound Method for Integer ProgrammingJun Wang, Mei Long, Duan Li. 642-645 [doi]
- Hybrid Dual-Operating-Mode PWM Based Sliding Mode Controllers for DC-DC ConvertersSiew-Chong Tan, Y. M. Lai. 646-649 [doi]
- Practical Implementation of Sliding Mode Control for Boost ConverterD. Seshachalam, R. K. Tripathi, D. Chandra. 650-653 [doi]
- Current-Mode Converters with Adjustable-Slope Compensating RampCheng-Chung Yang, Chen-Yu Wang, Tai-Haur Kuo. 654-657 [doi]
- Steady-State Performance Analysis of Cascade Boost ConvertersMiao Zhu, Fang Lin Luo. 658-661 [doi]
- A Monolithic Boost Converter with an Adaptable Current-Limited PFM SchemeHou-Ming Chen, Ding-Da Jiang, Robert C. Chang. 662-665 [doi]
- On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling TechnologyJen-Wei Yang, Po-Tsang Huang, Wei Hwang. 666-669 [doi]
- Embedded DC-DC Voltage Down Converter for Low-Power VLSI ChipQianneng Zhou, Fengchang Lai, Mingyan Yu. 670-673 [doi]
- Design of a Wireless Power Supply Receiver for Biomedical ApplicationsN. A. Samad, Tharshan Vaithianathan, Syed Mahfuzul Aziz, C. E. Brander. 674-677 [doi]
- A Novel DPWM Based on Fully Table Look-Up for High-Frequency Power ConversionMorris Ming-Hui Chiu, Steve Hung-Lung Tu. 678-681 [doi]
- An Implantable SOC Chip for Micro-stimulating and Neural Signal RecordingChua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, Cheng-Mu Wu, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng, Jia-Jin Chen. 682-685 [doi]
- A Novel Current Feed-back Sub-Nano-Siemen Transconductance Circuit Suitable for Large Time-Constant Bio-medical ApplicationsS. M. Rezaul Hasan, Nazmul Ula. 686-689 [doi]
- Design of Low-Frequency Low-Pass Filters for Biomedical ApplicationsChun-Lung Hsu, Mean-Hom Ho, Yu-Kuan Wu, Ting-Hsuan Chen. 690-695 [doi]
- A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal SensingChua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Kuan-Wen Fang. 696-699 [doi]
- Parallel Discovery of Transcription Factor Binding SitesA. Wirawan, B. Schmidt. 700-703 [doi]
- Low Power Bootstrapped CMOS Differential Cross Coupled DriverJosé C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi. 704-707 [doi]
- A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active FeedbackZhangcai Huang, Yasuaki Inoue, Hong Yu, Quan Zhang. 708-711 [doi]
- Two Novel Phase-Frequency DetectorsC. J. Kikkert. 712-715 [doi]
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- Fourier Series Analysis for Nonlinearities Due to the Power Supply Noise in Open-Loop Class D AmplifiersWei Shu, Joseph Sylvester Chang, Tong Ge, Meng Tong Tan. 720-723 [doi]
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- Impacts of Inductance on the Figures of Merit to Optimize Global InterconnectA. Roy, M. H. Chowdhury. 1422-1425 [doi]
- Optical Interconnect Technology; Photons Based Signal CommunicationG. Kshirsagar, M. H. Chowdhury. 1426-1429 [doi]
- Low Power Combinational Multipliers using Data-driven Signal GatingNima Honarmand, Ali Afzali-Kusha. 1430-1433 [doi]
- Synthesis of Finite State Machines for Low Power and TestabilityS. Chaudhury, S. Chattopadhyay, J. Srinivasa Rao. 1434-1437 [doi]
- An Efficient Self-Transposing Memory Structure for 32-bit Video ProcessorsMahdi Nazm Bojnordi, Naser Sedaghati-Mokhtari, Omid Fatemi, Mahmoud Reza Hashemi. 1438-1441 [doi]
- Highly Linear and Efficient AlGaAs/GaAs HBT Power Amplifier with Integrated LinearizerA. K. Mrunal, M. Shirasgaonkar, R. Patrikar. 1442-1445 [doi]
- A Fast Bit-Interleaving RSA Cryptosystem Based on Radix-4 Cellular-Array Modular MultiplierJin-Hua Hong, Bin-Yan Tsai. 1446-1449 [doi]
- A 1V 2.4GHz Down Conversion Folded MixerRo-Min Weng, Jing-Chyi Wang, Hung-Che Wei. 1450-1452 [doi]
- Analysis and Design of High Performance, Low Power Multiple Ports Register FilesTing-Sheng Jau, Wei-Bin Yang, Chung-Yu Chang. 1453-1456 [doi]
- Modeling a Digital Hearing Instrument for Developing and Evaluating Adaptive Feedback Cancellation AlgorithmsJingbo Yang. 1457-1460 [doi]
- On-Chip Supply Voltage Measurement TechniqueMa Fan Yung. 1461-1464 [doi]
- A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC DesignShan Gao, Junning Chen, Daoming Ke, Xiulong Wu. 1465-1468 [doi]
- The Setup of Artifical Neural Network Model for Estimating the Insulator Pollution DegreeLu Fangcheng, Zhang Zhongyuan, Huang Bin, Zhang Jianxing. 1469-1472 [doi]
- Low-Power Exponential V-I Converter Using Composite PMOS TransistorsRo-Min Weng, Xie-Ren Hsu. 1473-1475 [doi]
- Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS ProcessKwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen. 1476-1479 [doi]
- Simplification of Exclusive-or Sum-of-Products Expressions Through Function TransformationTakashi Hirayama, M. Takahashi, Yasuaki Nishitani. 1480-1483 [doi]
- 2PADCL: Two Phase drive Adiabatic Dynamic CMOS LogicYasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama. 1484-1487 [doi]
- Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL)A. K. Mrunal, M. A. Shirasgaonkar, R. Patrikar. 1488-1491 [doi]
- Low Complexity Architecture for Multiplicative Inversion in GF(2m)Ming-Haw Jing, Jian-Hong Chen, Zih-Heng Chen, Yan-Haw Chen. 1492-1495 [doi]
- An Area-Efficient Design for Modular Inversion in GF(2m)Jian Wang, Anping Jiang. 1496-1499 [doi]
- Physics-based Modeling and Simulation of Dual Material Gate(DMG) LDMOSYuehua Dai, Yuan Hu, Qi Liu, Daoming Ke, Junning Chen. 1500-1503 [doi]
- Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG LogicGopal Paul, S. N. Pradhan, Ajit Pal, Bhargab B. Bhattacharya. 1504-1507 [doi]
- Analysis and Measurement of Cross Modulation Distortion in WCDMA ReceiversS. K. Mohammed, Naveen K. Yanduru. 1508-1511 [doi]
- A High-Speed Low-Complexity VLSI SISO ArchitectureM. Nabipoor, S. A. Khodaian, Naser Sedaghati-Mokhtari, Sied Mehdi Fakhraie, Seyed Hamaidreza Jamali. 1512-1515 [doi]
- Frequency Synthesizer for Wireless Applications using TDTLAbdulrahman Al-Humaidan, Saleh R. Al-Araji, Mahmoud Al-Qutayri. 1516-1519 [doi]
- Adaptive ZCDPLL for Quadrature-Quadrature PSK Carrier RecoveryQ. Nasir. 1520-1522 [doi]
- Digital GFSK Carrier SynchronizationDah-Chung Chang, Tsung-Hau Shiu. 1523-1526 [doi]
- A Novel Neural Network GA-Optimized Controller for QoS Support in Wireless MACsZ. Pajouhi, Seid Mehdi Fakhraie. 1527-1530 [doi]
- Performance Analysis of Successive Interference Cancellation in Multiuser CDMA over Flat ChannelsKok Ann Donny Teo, Shuichi Ohno. 1531-1534 [doi]
- Reduced-Complexity Concurrent Systolic Implementation of the Discrete Sine TransformPramod Kumar Meher, A. Prasad Vinod, Jagdish Chandra Patra, M. N. S. Swamy. 1535-1538 [doi]
- Area/Delay Efficient Recoding Methods for Parallel CORDIC RotationsTso-Bing Juang. 1539-1542 [doi]
- Ultra Low Power Weak Inversion Current Steered Digital to Analog ConverterDavid Fitrio, Aleksandar Stojcevski, Jugdutt Singh. 1543-1546 [doi]
- Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity AnalysisA. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla. 1547-1550 [doi]
- Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - AlgorithmA. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla. 1551-1554 [doi]
- A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless FiltersUwe Meyer-Bäse, Jiajia Chen, Chip-Hong Chang, Andrew G. Dempster. 1555-1558 [doi]
- A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric KernelsMing Z. Zhang, Vijayan K. Asari. 1559-1562 [doi]
- Constructing Better Partial Sums Based on Energy-Maximum Criterion for Fast Encoding of VQZhibin Pan, Tadahiro Ohmi, Koji Kotani. 1563-1566 [doi]
- A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding SystemShao-Ming Sun, Tsu-Ming Liu, Chen-Yi Lee. 1567-1570 [doi]
- A Quick Scene Search with Constructed Mapped Charts for TV Sport ProgramsT. Fuangrod, A. Khawne. 1571-1574 [doi]
- Accelearation of Full-Search Algorithm on SIMD Architectures by Using Eight-Bit Partial Sums of Four Luminance ValuesC. J. Duanmu. 1575-1578 [doi]
- A Fast Hexagon-Based Search Algorithm on SIMD ArchitecturesC. J. Duanmu. 1579-1582 [doi]
- Robust Scalable Video Transmission using Object-Oriented Unequal Loss Protection over InternetZhen Qiu, Takeshi Ikenaga, Satoshi Goto. 1583-1586 [doi]
- The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions DetectionChung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei. 1587-1590 [doi]
- A Novel Input Stage Based on DTMOS for Low-Voltage Low-Noise Operational AmplifierZhiyuan Li, Mingyan Yu, Jianguo Ma. 1591-1594 [doi]
- A Frequency Compensation Technique for Variable Output Low Dropout RegulatorsAkira Yamazaki, Kouhei Yamada, Satoshi Sugahara. 1595-1598 [doi]
- Design and Analysis of a VHF OTA-C Cell for Optimum Phase ResponseKshitij Yadav, Pradip Mandal. 1599-1602 [doi]
- Separation of Individual Noise Sources from Compound Noise Measurements in Digital CircuitsV. P. Nigam, Masud H. Chowdhury, Roland Priemer. 1603-1606 [doi]
- Model-Order Reduction Algorithm with Structure Preserving TechniquesMing-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng. 1607-1610 [doi]
- Low-Power Crosstalk Avoidance Encoding for On-Chip Data BusesQingli Zhang, Jinxiang Wang, Yizheng Ye. 1611-1614 [doi]
- Sensitivity Analysis of Uniform and Nonuniform Transmission LinesLiang Guishu, Dong Huaying, Wang Yong, Zhang Zhongyuan, Lu Fangcheng. 1615-1618 [doi]
- Operation Scheduling for False Loop Free CircuitsShih-Hsu Huang, Chun-Hua Cheng. 1619-1622 [doi]
- Fixed Polarity Arithmetic Expansions Calculation from Disjoint Cubes Representation of Ternary FunctionsCicilia C. Lozano, Bogdan J. Falkowski. 1623-1626 [doi]
- Disjoint Cubes Generation Algorithm for Multiple-Valued FunctionsBogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja. 1627-1630 [doi]
- Efficient Pass-Transistor-Logic Synthesis for Sequential CircuitsShen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen. 1631-1634 [doi]
- Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor PolynomialsQiang Zhou, Yi Zou, Yici Cai, Xianlong Hong. 1635-1638 [doi]
- A Method for the Correction of N-Ports Scattering Parameters MeasurementBaishan Zhao, Yi-Sheng Zhu. 1639-1642 [doi]
- Fast Conversion for Large Canonical OR-Coincidence FunctionsM. Yang, L. Wang, A. E. A. Almaini. 1643-1646 [doi]
- A Simple Synthesis Technique of PWM SignalWasu Phanphaisarn, Sukkharak Saechia. 1647-1650 [doi]
- Real-Time Image Stabilization for Digital Video CamerasWen-Chung Kao, Shou-Hung Chen, Pei-Yung Hsiao. 1651-1654 [doi]
- Unified Signed-Digit Number Adder for RSA and ECC Public-key CryptosystemsYi Wang, Douglas L. Maskell, Jussipekka Leiwo, Thambipillai Srikanthan. 1655-1658 [doi]
- An Efficient Algorithm for DPA-resistent RSAYi Wang, Jussipekka Leiwo, Thambipillai Srikanthan, Luo Jianwen. 1659-1662 [doi]
- A 1.6GHz Downconverter Mixer in 0.25µm CMOSF. J. Antunes, Tales Cleber Pimenta, Robson L. Moreno. 1663-1666 [doi]
- Translinear Loop Principle and Identification of the Translinear LoopsCheng Yuhua, Wu Xiaobo, Yan Xiaolang. 1667-1670 [doi]
- A 12-bit CMOS Current Steering D/A Converter for Embedded SystemsJesús Ruiz-Amaya, Manuel Delgado-Restituto, Juan Francisco Fernández-Bootello, D. Brandano, R. Castro-López, José Manuel de la Rosa. 1671-1674 [doi]
- An FPGA Implementation of Array LDPC DecoderJin Sha, Ming-Lun Gao, Zhongjin Zhang, Li Li, Zhongfeng Wang. 1675-1678 [doi]
- A 2.4-GHz CMOS Tunable Image-Rejection Low-Noise Amplifier with Active InductorLer Chun Lee, Abu Khari bin A ain, A. V. Kordesch. 1679-1682 [doi]
- A Real-time Boat Surveillance System Using GPRSYang Jie, Zhou Changzheng, Zhang Qingnian, Zhou Zhizhong. 1683-1686 [doi]
- Non-Data Aided SBIB ReceiverTsui-Tsai Lin. 1687-1690 [doi]
- Single Amplifier Sigma Delta Modulator With Input FeedforwardXiaolong Yuan, S. Signed, Xiaobo Wu. 1691-1694 [doi]
- A Tunable Ultra-Wideband Pulse Generator Using a Variable Edge-Rate SignalErick Maxwell, Thomas Weller, Jeffrey Harrow. 1695-1698 [doi]
- Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLANWei Zhong, Zhigang Mao. 1699-1702 [doi]
- The Design of Anti-collision Mechanism of UHF RFID System based on CDMAPing Wang, Aiqun Hu, Wenjiang Pei. 1703-1708 [doi]
- On The Realization of Active MURC Filter wth a Single Pole AmplifierS. Wachirarattanapornkul. 1709-1712 [doi]
- Error Concealment Using Digital WatermarkingM. Jayalakshmi, S. N. Merchant, Uday B. Desai, G. Ajay, J. V. L. Aanchan, P. Srinath, J. Shashank. 1713-1716 [doi]
- An Iterative Super-Resolution Reconstruction of Image Sequences using Fast Affine Block-Based Registration with BTV RegularizationVorapoj Patanavijit, Somchai Jitapunkul. 1717-1720 [doi]
- Power Consumption in Handheld ComputersAssim Sagahyroon. 1721-1724 [doi]
- From Software to Hardware - A Novel TLM Auto-Generating MethodLiang Zhu, Jinian Bian. 1725-1728 [doi]
- Improved Robust Multiuser Detection in Non-Gaussian Channels Using a New M-Estimator and Spatiotemporal Chaotic Spreading SequencesK. Deergha Rao, B. V. S. S. N. Raju. 1729-1732 [doi]
- Generation of Panoramic Image from Aerial Video utilizing JP2K Wavelet for River SurveillanceMasahiro Iwahashi, Sakol Udomsiri, Jyun Watanabe, Shinji Fukuma. 1733-1736 [doi]
- A Harmonic Reduction Scheme in SPWMHirak Patangia, Dennis Gregory. 1737-1740 [doi]
- Water Level Detection for River Surveillance utilizing JP2K Wavelet TransformMasahiro Iwahashi, Sakol Udomsiri, Yuji Imai, Shinji Fukuma. 1741-1744 [doi]
- Dual Mode Architecture for Deblocking Filtering in H.264/AVC Video CodingMahdi Nazm Bojnordi, Omid Fatemi, Mahmoud Reza Hashemi. 1745-1748 [doi]
- Efficient Hardware Implementation for H.264/AVC Motion EstimationMahdi Nazm Bojnordi, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Omid Fatemi. 1749-1752 [doi]
- Design and Implementation of a 2-level FSK Digital Modems Using CORDIC AlgorithmXiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui. 1753-1756 [doi]
- Power Management in Circuits DesignTianchi Yang, Liang Jin, Juan Chen. 1757-1759 [doi]
- A Novel Structure of Conjunction Decision Feedback Equalizer for Nonlinear ChannelsHaiquan Zhao, Mingyuan Xie, Xiangping Zeng. 1760-1763 [doi]
- A Novel Method for Systematic Error Prediction of CMOS Folding and Interpolating ADCMasoud Babaie, Hamid Movahedian, Mehrdad Sharif Bakhtiar. 1768-1771 [doi]
- Low Voltage Analogue MultiplierSaurabh Singh, K. Radhakrishna Rao. 1772-1775 [doi]
- A Low-power Tunable Bandpass Amplifier for RF ApplicationsKun-Yi Lin, Ro-Min Weng. 1776-1778 [doi]
- Low Voltage High-Performance Class-AB FGMOS BufferKornika Moolpho, Jitkasame Ngarmnil. 1779-1782 [doi]
- Electrocardiogram Analysis with Adaptive Feature Selection and Support Vector MachinesWen-Chung Kao, Chun-Kuo Yu, Chia-Ping Shen, Wei-Hsin Chen, Pei-Yung Hsiao. 1783-1786 [doi]
- Optimizing High Speed Flip-Flop Using Genetic AlgorithmFatemeh Aezinia, Ali Afzali-Kusha, Caro Lucas. 1787-1790 [doi]
- Engery-Efficient Double-Edge Triggered Flip-Flop DesignChua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen. 1791-1794 [doi]
- A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET DevicesSaihua Lin, Rong Luo, Huazhong Yang, Hui Wang. 1795-1798 [doi]
- Another Look at the Sequential Multiplier over Normal BasesZih-Heng Chen, Ming-Haw Jing, Trieu-Kien Truong, Yaotsu Chang. 1799-1802 [doi]
- A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD EnvironmentMasanori Hariyama, Michitaka Kameyama. 1803-1806 [doi]
- Level Selection Based 4-PAM Transmitter for Chip to Chip CommunicationKang-Yu Chang, Zhi-Ming Lin. 1807-1810 [doi]
- Research of Phase-Inversion Symmetric Modulation Based on DSB Communication SystemXiao Baojin, Xiao Yingzhe, Xiao Baowei. 1811-1813 [doi]
- Digital Audio Broadcasting System Modeling and Hardware ImplementationNariman Moezzi Madani, Hamed Holisaz, Seid Mehdi Fakhraie. 1814-1817 [doi]
- Rapid Acquisition of Ultra-Wideband Signals in Multipath EnvironmentsAhmad Saghafi, Seid Mehdi Fakhraie. 1818-1821 [doi]
- Digital Network Echo Cancellation Using Genetic Algorithm and Combined GA-LMS MethodNeda Kazemian Amiri, Seid Mehdi Fakhraie. 1822-1825 [doi]
- Chua Circuit Based Reconfigurable Computing SystemMohammad-Reza Jahed Motlagh, Behnam Kia. 1826-1829 [doi]
- Unscented Kalman Filter and Particle Filter for Chaotic SynchronizationAjeesh P. Kurian, Sadasivan Puthusserypady. 1830-1834 [doi]
- Exploiting Chaos for ComputationWilliam L. Ditto, K. Murali, Sudeshna Sinha. 1835-1838 [doi]
- Reconfigurable Logic Element using a Chaotic CircuitK. Murali, Sudeshna Sinha, William L. Ditto. 1839-1842 [doi]
- Exploiting Nonlinear Dynamics to Search for the Existence of Matches in a DatabaseAbraham Miliotis, William L. Ditto, Sudeshna Sinha. 1843-1846 [doi]
- Codeblock-Based Concealment Scheme for JPEG2000 Images in Lossy Packet NetworksKhairul Munadi, Masaaki Fujiyoshi, Kiyoshi Nishikawa, Hitoshi Kiya. 1847-1850 [doi]
- Progressive Technique for Rate Distortion Optimization in JPEG2000Yizhen Zhang, Chao Xu. 1851-1854 [doi]
- 4K SHD Real-Time Video Streaming System With JPEG 2000 Parallel CodecDaisuke Shirai, Takahiro Yamaguchi, Takashi Shimizu, Takahiro Murooka, Tetsuro Fujii. 1855-1858 [doi]
- Application of Multi-ported CAM for Parallel CodingTakeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch. 1859-1862 [doi]
- A Novel Hybrid Approach of Color Image SegmentationYangxing Liu, Takeshi Ikenaga, Satoshi Goto. 1863-1866 [doi]
- On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good ConvergenceSong Chen, Takeshi Yoshimura. 1867-1870 [doi]
- Thermal Driven Module Placement Using Sequence-pairN. Okada, Chikaaki Kodama, T. Sato, Kunihiro Fujiyoshi. 1871-1874 [doi]
- Efficient Algorithms for Hardware/Software Partitioning to Minimize Hardware AreaWu Jigang, Thambipillai Srikanthan. 1875-1878 [doi]
- Global Interconnect Analysis and Optimization for Nanometer Scale VLSILele Jiang, Junfa Mao. 1879-1882 [doi]
- A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI CircuitsJiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu. 1883-1886 [doi]
- Reducing Noisy-Coefficient Problem in Non-Continuous Adaptive Feedback Canceller for Hearing AidsJingbo Yang. 1887-1890 [doi]
- A Robust Correlation Method for Solving Permutation Problem in Frequency Domain Blind Source Separation of Speech SignalsV. G. Reju, Soo Ngee Koh, Ing Yann Soon. 1891-1894 [doi]
- Blind Determination of the Signal to Noise Ratio of Speech Signals Based on Estimation Combination of Multiple FeaturesR. Ondusko, M. Marbach, A. McClellan, R. P. Ramachandran, L. M. Head, M. C. Huggins, Brett Y. Smolenski. 1895-1898 [doi]
- Design of IP Media Server for Voice Conference ApplicationQing Wang, Zhenbo Zhu, Yi Ge, Ling Shao. 1899-1902 [doi]
- Implementation of MPEG-2 AAC on 16-bit Fixed-Point DSPHui Wang, Wenbin Xu, Xin Dong, Chuanzhen Li, Wenhua Yu. 1903-1906 [doi]
- DWDM Demultiplexer Using Compound Optical Ring Resonator with Fiber Bragg GratingSommart Sang-Ngern, A. Roeksabutr. 1907-1910 [doi]
- Optical Front-Ends for Low-Cost Laser-Based 10-Mbps Free-Space Optical TransceiverPhanumas Khumsat, Noppadol Wattanapisit, Karel Kulhavey. 1911-1914 [doi]
- A Standalone Printing USB Host Device PrototypePeter K. K. Loh. 1915-1918 [doi]
- Narrow-Band FM Multi-Tone FSK Modem: TMS320C6000 Based Testbed Implementation and Performance AnalysisKandeepan Sithamparanathan, Yong Kang Wong. 1919-1922 [doi]
- Genetic Algorithm based Approximants for Discrete Time Systems: A Computer-Aided ApproachN. L. Prajapati, D. Chandra. 1923-1926 [doi]
- A 2-D Systolic Array for High-Throughput Computation of 2-D Discrete Fourier TransformPramod Kumar Meher, Jagdish Chandra Patra, A. Prasad Vinod. 1927-1930 [doi]
- A Low-Power Reconfigurable Mixed-Radix FFT/IFFT ProcessorChi-Chen Lai, Wei Hwang. 1931-1934 [doi]
- A Low Multiplier and Multiplication Costs 256-point FFT Implementation with Simplified Radix-24 SDF ArchitectureChih-Peng Fan, Mau-Shih Lee, Guo-An Su. 1935-1938 [doi]
- A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed OutputsChih-Peng Fan, Guo-An Su. 1939-1942 [doi]
- A Discrete STFT Processor for Real-time Spectrum AnalysisShiqun Zhang, Dunshan Yu, Shimin Sheng. 1943-1946 [doi]
- A Low Cost/Low Power Chaos-based Transceiver Exploiting ErgodicityD. Majumdar, W. Li, H. Leung, B. J. Maundy. 1947-1950 [doi]
- Look-up Table Based Chaotic Encryption of Audio FilesK. Ganesan, R. Muthukumar, K. Murali. 1951-1954 [doi]
- Design of A Low Power High Entropy Chaos-Based Truly Random Number GeneratorTong Zhou, Zhibo Zhou, Mingyan Yu, Yizheng Ye. 1955-1958 [doi]
- A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear WaveformsDaisuke Atuti, Takashi Morie, K. Aihara. 1959-1963 [doi]
- Chaos Synchronization Using A Robust Sliding Mode Observer By Transmitting A Scalar SignalLixia Sun, Ping Qu, Yong Feng. 1964-1967 [doi]
- A New Multiscale Line Detection Approach for Aerial Image with Complex SceneJaidong Wang, Takeshi Ikenaga, Satoshi Goto, Kazuo Kunieda, M. Iwata, H. Koizumi, H. Shimazu. 1968-1971 [doi]
- A Display Order Oriented Scalable Video DecoderJia-Bin Huang, Yu-Kun Lin, Tian-Sheuan Chang. 1976-1979 [doi]
- Implementation of Multipoint Video Conference in SoftwareYang Jie, Shen Sun. 1980-1983 [doi]
- An Improved SVD-Based Watermarking Technique for Image and Document AuthenticationJagdish Chandra Patra, W. Soh, Ee-Luang Ang, Pramod Kumar Meher. 1984-1987 [doi]
- Study on Complex Behavior in Phase-Shifting Full-Bridge ZVS ConverterXin-huai Chen, Yufei Zhou, Jun-Ning Chen, Li-li Wang. 1988-1991 [doi]
- Uncertainty Management for Estimation in Dynamical SystemsH. Baili. 1992-1995 [doi]
- Nonlinear STATCOM Controller using Passivity-Based Sliding Mode ControlHung-Chi Tsai, Chia-Chi Chu. 1996-1999 [doi]
- Frequency Interval Gramians based Model ReductionAbdul Ghafoor, Victor Sreeram. 2000-2003 [doi]
- Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale CircuitsC. M. Tan, M. H. Chowdhury. 2004-2007 [doi]
- A Simulink-to-FPGA Co-Design of Encryption ModuleXiaoying Li, Fuming Sun, Enhua Wu. 2008-2011 [doi]
- Analytic Solution of Amplitude Controlled Digital Oscillator Using Multi-Time Variables TechniqueR. Punchalard, Jeerasuda Koseeyaporn, Paramote Wardkein. 2012-2015 [doi]
- Reduced-Dimension Single Data Set Detection AlgorithmsChin-Heng Lim. 2016-2019 [doi]
- Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1)Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu. 2020-2023 [doi]
- Online Continues Vietnamese Handwritten Character Recognition Based on Microsoft Handwritten Character Recognition LibraryNgo Quoc Tao, Pham Van Hung. 2024-2026 [doi]