Abstract is missing.
- Short Division of Long IntegersDavid Harvey, Paul Zimmermann. 7-14 [doi]
- High Degree Toom n Half for Balanced and Unbalanced MultiplicationMarco Bodrato. 15-22 [doi]
- Augmented Precision Square Roots and 2-D Norms, and Discussion on Correctly Rounding sqrt(x^2+y^2)Nicolas Brisebarre, Mioara Joldes, Peter Kornerup, Érik Martin-Dorel, Jean-Michel Muller. 23-30 [doi]
- Towards a Quaternion Complex Logarithmic Number SystemMark G. Arnold, John R. Cowles, Vassilis Paliouras, Ioannis Kouretas. 33-42 [doi]
- ROM-less LNSR. Che Ismail, J. N. Coleman. 43-51 [doi]
- Composite Iterative Algorithm and Architecture for q-th Root CalculationAlvaro V zquez, Javier D. Bruguera. 52-61 [doi]
- On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC MultipliersOmid Sarbishei, Katarzyna Radecka. 62-69 [doi]
- Self Checking in Current Floating-Point UnitsDaniel Lipetz, Eric Schwarz. 73-76 [doi]
- How to Square Floats Accurately and Efficiently on the ST231 Integer ProcessorClaude-Pierre Jeannerod, Jingyan Jourdan-Lu, Christophe Monat, Guillaume Revy. 77-81 [doi]
- A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOSTimothy Anderson, Duc Bui, Shriram Moharil, Soujanya Narnur, Mujibur Rahman, Anthony Lell, Eric Biscondi, Ashish Shrivastava, Peter Dent, Mingjian Yan, Hasan Mahmood. 82-86 [doi]
- The POWER7 Binary Floating-Point UnitMaarten Boersma, Michael Kroener, Christophe Layer, Petra Leber, Silvia M. Müller, Kerstin Schelm. 87-91 [doi]
- Accelerating Computations on FPGA Carry Chains by Operand CompactionThomas B. Preußer, Martin Zabel, Rainer G. Spallek. 95-102 [doi]
- Fast Ripple-Carry Adders in Standard-Cell CMOS VLSINeil Burgess. 103-111 [doi]
- A Family of High Radix Signed Digit AddersSaeid Gorgin, Ghassem Jaberipur. 112-120 [doi]
- Fused Multiply-Add Microarchitecture Comprising Separate Early-Normalizing Multiply and Add PipelinesDavid R. Lutz. 123-128 [doi]
- Latency Sensitive FMA DesignSameh Galal, Mark Horowitz. 129-138 [doi]
- The IBM zEnterprise-196 Decimal Floating-Point AcceleratorSteven R. Carlough, Adam Collura, Silvia M. Müller, Michael Kroener. 139-146 [doi]
- Radix-8 Digit-by-Rounding: Achieving High-Performance Reciprocals, Square Roots, and Reciprocal Square RootsJ. Adam Butts, Ping Tak Peter Tang, Ron O. Dror, David E. Shaw. 149-158 [doi]
- Tight Certification Techniques for Digit-by-Rounding Algorithms with Application to a New 1/sqrt(x) DesignPing Tak Peter Tang, J. Adam Butts, Ron O. Dror, David E. Shaw. 159-168 [doi]
- Radix-16 Combined Division and Square Root UnitAlberto Nannarelli. 169-176 [doi]
- A Prescale-Lookup-Postscale Additive Procedure for Obtaining a Single Precision Ulp Accurate ReciprocalDavid W. Matula, Mihai T. Panu. 177-183 [doi]
- Teraflop FPGA DesignMartin Langhammer. 187-188 [doi]
- The Arithmetic Operators You Will Never See in a MicroprocessorFlorent de Dinechin. 189-190 [doi]
- Accelerating Large-Scale HPC Applications Using FPGAsRobert G. Dimond, Sebastien Racanière, Oliver Pell. 191-192 [doi]
- A General Approach for Improving RNS Montgomery Exponentiation Using Pre-processingFilippo Gandino, Fabrizio Lamberti, Paolo Montuschi, Jean-Claude Bajard. 195-204 [doi]
- Bit-Sliced Binary Normal Basis MultiplicationBilly Bob Brumley, Dan Page. 205-212 [doi]
- Efficient SIMD Arithmetic Modulo a Mersenne NumberJoppe W. Bos, Thorsten Kleinjung, Arjen K. Lenstra, Peter L. Montgomery. 213-221 [doi]
- Automatic Generation of Code for the Evaluation of Constant Expressions at Any Precision with a Guaranteed Error BoundSylvain Chevillard. 225-232 [doi]
- Automatic Generation of Fast and Certified Code for Polynomial EvaluationChristophe Mouilleron, Guillaume Revy. 233-242 [doi]
- Flocq: A Unified Library for Proving Floating-Point Algorithms in CoqSylvie Boldo, Guillaume Melquiond. 243-252 [doi]