Abstract is missing.
- Parallelizing HMMER for Hardware Acceleration on FPGAsSteven Derrien, Patrice Quinton. 10-17 [doi]
- FPGA-Based Efficient Design Approach for Large-Size Two s Complement SquarersShuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois. 18-23 [doi]
- A Self-Reconfigurable Implementation of the JPEG EncoderAntonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 24-29 [doi]
- Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable ComputersJahyun J. Koo, David Fernández, Ashraf Haddad, Warren J. Gross. 30-35 [doi]
- Windowed FIFOs for FPGA-based Multiprocessor SystemsKai Huang, D. Grunert, Lothar Thiele. 36-41 [doi]
- Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC FabricsHaibo Zhu, Partha Pratim Pande, Cristian Grecu. 42-47 [doi]
- Transaction Specific Virtual Channel Allocation in QoS Supported On-chip CommunicationMohammad Abdullah Al Faruque, Jörg Henkel. 48-53 [doi]
- Scalable Multi-FPGA Platform for Networks-On-Chip EmulationAbdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur Senouci, Frédéric Pétrot. 54-60 [doi]
- Mapping and Topology Customization Approaches for Application-Specific STNoC DesignsGianluca Palermo, Giovanni Mariani, Cristina Silvano, Riccardo Locatelli, Marcello Coppola. 61-68 [doi]
- Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip RouterSumit D. Mediratta, Jeffrey T. Draper. 69-75 [doi]
- Real-time FPGA-implementation for blue-sky DetectionNhut Thanh Quach, Bahman Zafarifar, Georgi Gaydadjiev. 76-82 [doi]
- An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point AdderNikhil Kikkeri, Peter-Michael Seidel. 83-88 [doi]
- Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable ProcessorsSiew Kei Lam, Thambipillai Srikanthan. 89-94 [doi]
- FPGA SAR Processor with Window Memory AccessesYong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou. 95-100 [doi]
- The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable HardwareSherman Braganza, Miriam Leeser. 101-106 [doi]
- LNS Subtraction Using Novel Cotransformation and/or InterpolationPanagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold. 107-114 [doi]
- Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding UnitCharles Tsen, Michael J. Schulte, Sonia Gonzalez-Navarro. 115-121 [doi]
- A Hardware-Oriented Method for Evaluating Complex PolynomialsMilos D. Ercegovac, Jean-Michel Muller. 122-127 [doi]
- Power6 Decimal DivideEric M. Schwarz, Steven R. Carlough. 128-133 [doi]
- Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2:::m:::)Pramod Kumar Meher. 134-139 [doi]
- Scheduling Register-Allocated Codes in User-Guided High-Level SynthesisAlain Darte, C. Quinson. 140-147 [doi]
- Design Flow of a Dedicated Computer Cluster Customized for a Distributed Genetic Algorithm ApplicationA. Aguiar, M. Kreutz, R. Santos, T. Santos. 148-153 [doi]
- A Compact Fading Channel Simulator Using Timing-Driven Resource SharingAmirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel. 154-159 [doi]
- 0/1 Knapsack on Hardware: A Complete SolutionK. Nibbelink, S. Rajopadhye, R. McConnell. 160-167 [doi]
- Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo SimulationsDavid B. Thomas, Jacob A. Bower, Wayne Luk. 168-173 [doi]
- SIMD Vectorization of Histogram FunctionsAsadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis. 174-179 [doi]
- A Run-Time Reconfigurable Fabric for 3D Texture FilteringWei-Ting Wang, Yi-Chi Chen, Chung-Ping Chung. 180-185 [doi]
- Reconfigurable Universal AdderHumberto Calderon, Georgi Gaydadjiev, Stamatis Vassiliadis. 186-191 [doi]
- A Triplet-based Computer Architecture Supporting Parallel Object ComputingFeng Shi, Weixing Ji, Baojun Qiao, Bin Liu, Haroon-ul-Rashid. 192-197 [doi]
- The Design of a Novel Object-oriented Processor : OOMIPSWeixing Ji, Feng Shi, Baojun Qiao, Muhammad Kamran. 198-203 [doi]
- Run-Time Error Detection in Polynomial Basis Multiplication Using Linear CodesSiavash Bayat Sarmadi, M. Anwar Hasan. 204-209 [doi]
- Customizing Reconfigurable On-Chip Crossbar SchedulerJae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis. 210-215 [doi]
- Design and Implementation of an Efficient and Power-Aware Architecture for Skin Segmentation in Color Video StreamHau T. Ngo, Satyanadh Gundimada, Vijayan K. Asari. 216-221 [doi]
- Entropy Coding on a Programmable Processor Array for Multimedia SoCRoberto R. Osorio, Javier D. Bruguera. 222-227 [doi]
- Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-MultiprocessorsXiongfei Liao, Wu Jigang, Thambipillai Srikanthan. 228-233 [doi]
- Design and implementation of a surface peak thermal detector algorithmC. Boustany, Ahmed Lakhsasi, Mohammed Bougataya. 234-238 [doi]
- A High-Throughput Programmable Decoder for LDPC Convolutional CodesMarcel Bimberg, Marcos B. S. Tavares, Emil Matús, Gerhard Fettweis. 239-246 [doi]
- A Novel Low-Power Motion Estimation Design for H.264Maria G. Koziri, A. N. Dadaliaris, Georgios I. Stamoulis, Ioannis Katsavounidis. 247-252 [doi]
- Reconfigurable Motion Estimation Architecture for Multi-standard Video CompressionLiang Lu, John V. McCanny, Sakir Sezer. 253-259 [doi]
- An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video CodingJianying Peng, Xing Qin, Dexian Li, Xiaolang Yan, Xiexiong Chen. 260-265 [doi]
- Reduced Delay BCD AdderA. A. Bayrakci, A. Akkas. 266-271 [doi]
- Improving the Throughput of On-line Addition for Data StreamsJulio Villalba, Javier Hormigo, Tomás Lang. 272-277 [doi]
- Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming!Walid Ibrahim, Valeriu Beiu. 278-283 [doi]
- Computing Digit Selection Regions for Digit RecurrencesD. K. Wilde. 284-289 [doi]
- Hardware Acceleration for 3-D Radiation Dose CalculationBo Zhou, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X. Yu. 290-295 [doi]
- Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS ReceiversGötz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll. 296-301 [doi]
- Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global RoutingStephan Bourduas, Zeljko Zilic. 302-307 [doi]
- Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing PerspectiveBen Cope, Peter Y. K. Cheung, Wayne Luk. 308-313 [doi]
- Two-level tiling for MPSoC architectureYoucef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu. 314-319 [doi]
- Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication SystemsSuman Mamidi, Michael J. Schulte, Daniel Iancu, C. John Glossner. 320-327 [doi]
- Identification of Application Specific Instructions Based on Sub-Graph Isomorphism ConstraintsChristophe Wolinski, Krzysztof Kuchcinski. 328-333 [doi]
- A Retargetable Framework for Automated Discovery of Custom InstructionsPaolo Bonzini, Laura Pozzi. 334-341 [doi]
- A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System ExtensionsMahzad Azarmehr, Roberto Muscedere. 342-345 [doi]
- A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register AllocationJie Guo, Jun Liu, B. Mennenga, Gerhard Fettweis. 346-352 [doi]
- An Application Specific Memory Characterization Technique for Co-processor AcceleratorsSadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith. 353-358 [doi]
- GISP: A Transparent Superpage Support Framework for LinuxNing Qu, Yansong Zheng, Wei Cao, Xu Cheng. 359-364 [doi]
- Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based ApplicationsDavid Montgomery, Ali Akoglu. 365-370 [doi]
- A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW ArchitectureZhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng. 371-376 [doi]
- Graphic processors to speed-up simulations for the design of high performance solar receptorsSylvain Collange, Marc Daumas, David Defour. 377-382 [doi]
- Memory Operation Inclusive Instruction-Set Extensions and Data Path GenerationImyong Lee, Dongwook Lee, Kiyoung Choi. 383-390 [doi]
- Robust Adders Based on Quantum-Dot Cellular AutomataIsmo Hänninen, Jarmo Takala. 391-396 [doi]
- A memcpy Hardware Accelerator Solution for Non Cache-line Aligned CopiesFilipa Duarte, Stephan Wong. 397-402 [doi]
- A Rapid Prototyping Platform for Wireless Medium Access Control ProtocolsD. A. Armstrong, M. W. Pearson. 403-408 [doi]
- An Efficient Hardware Support for Control Data ValidationYong-Joon Park, Zhao Zhang, Gyungho Lee. 409-414 [doi]
- ISA Support for Fingerprinting and Erasure CodesWilliam Josephson, Ruby Lee, Kai Li. 415-422 [doi]