Table of Contents

• Co-evaluation of FPGA architectures and the CAD system for telecommunicationTsunemasa Hayashi, Atsushi Takahara, Ken-nosuke Fukami. 1-8 [doi]
• Performance test of Viterbi decoder for wideband CDMA systemJang-Hyun Park, Yea-Chul Rho. 19-23 [doi]
• Delay estimation for technology independent synthesisYutaka Tamiya. 31-36 [doi]
• Performance and reliability driven clock scheduling of sequential logic circuitsAtsushi Takahashi, Yoji Kajitani. 37-42 [doi]
• CBLO: a clustering based linear ordering for netlist partitioningKwang-Su Seong, Chong-Min Kyung. 43-48 [doi]
• Design driven partitioningDirk Behrens, Erich Barke, Robert Tolkiehn. 49-55 [doi]
• Acceleration of mincut partitioning using hardware CAD accelerator TP5000Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose. 61-64 [doi]
• Computing brokerage and its application in VLSI designYoun-Long Lin. 65-69 [doi]
• A high performance FIR filter dedicated to digital video transmissionShun Morikawa, Keisuke Okada, Sumitaka Takeuchi, Isao Shirakawa. 77-82 [doi]
• Structural approach for performance driven ECC circuit synthesisChauchin Su, E. Y. Chen, Shyh-Jye Jou. 89-94 [doi]
• An entropy measure for power estimation of Boolean functionsChi-Hong Hwang, Allen C.-H. Wu. 101-106 [doi]
• An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuitsKai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita. 107-112 [doi]
• A power driven two-level logic optimizerJyh-Mou Tseng, Jing-Yang Jou. 113-116 [doi]
• A note on the relationship between signal probability and switching activityQing Wu, Massoud Pedram, Xunwei Wu. 117-120 [doi]
• A new layout-driven timing model for incremental layout optimizationFang-Jou Liu, John Lillis, Chung-Kuan Cheng. 127-131 [doi]
• Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIsTetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru. 133-140 [doi]
• TM in electronic design automationPeter B. Denyer, Jean Brouwers. 141-144 [doi]
• Synthesis and analysis of an industrial embedded microcontrollerIng-Jer Huang, Li-Rong Wang, Yu-Min Wang. 151-156 [doi]
• Property verification in the design of telecom applicationsMassimo Bombana, Patrizia Cavalloro, Fabrizio Ferrandi. 167-172 [doi]
• Verification methodology of compatible microprocessorsJoon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee Choul Lee, Hoon Choi, Tae Hoon Kim, Seungjong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park, Chong-Min Kyung. 173-180 [doi]
• RTL verification of timed asynchronous and heterogeneous systems using symbolic model checkingVida Vakilotojar, Peter A. Beerel. 181-188 [doi]
• CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuitsWen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu. 189-194 [doi]
• Power consumption in CMOS combinational logic blocks at high frequenciesSri Parameswaran, Hui Guo. 195-200 [doi]
• A new approach for an AHDL based on system semanticsYoucef Bourai, Nouma Izeboudjen, Yacine Bouhabel, Amine Tafat. 201-206 [doi]
• EMC-adequate design of printed circuit boards as a part of the system developmentWerner John. 207-214 [doi]
• Crosstalk noise in high density and high speed interconnections due to inductive couplingTetsuhisa Mido, Kunihiro Asada. 215-220 [doi]
• MULTI-PRIDE: a system for supporting multi-layered printed wiring board designToshimasa Watanabe. 221-226 [doi]
• Embedded architectural simulation within behavioral synthesis environmentAbderrazek Jemai, Polen Kission, Ahmed Amine Jerraya. 227-232 [doi]
• Evaluating cost-performance tradeoffs for system level applicationsWei-Liang Ing, Cheng-Tsung Hwang, Allen C.-H. Wu. 233-238 [doi]
• A quantitative analysis for optimizing memory allocationYoun-Sik Hong, Choong-Hee Cho, Daniel D. Gajski. 239-245 [doi]
• Concurrent cell generation and mapping for CMOS logic circuitsM. Kanecko, Jialin Tian. 247-252 [doi]
• Logic synthesis for cellular architecture FPGAs using BDDsGueesang Lee. 253-258 [doi]
• BDD based lambda set selection in Roth-Karp decomposition for LUT architectureJie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei. 259-264 [doi]
• General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structureMaggie Zhiwei Kang, Wayne Wei-Ming Dai. 265-270 [doi]
• A building block placement toolJonathan Dufour, Robert McBride, Ping Zhang 0001, Chung-Kuan Cheng. 271-276 [doi]
• VEAP: Global optimization based efficient algorithm for VLSI placementTianming Kong, Xianlong Hong, Changge Qiao. 277-280 [doi]
• Hardware-software co-design: Tools for architecting systems-on-a-chipRajaesh K. Gupta. 285-289 [doi]
• Trade-off evaluation in embedded system design via co-simulationClaudio Passerone, Luciano Lavagno, Claudio Sansoè, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli. 291-297 [doi]
• A transformational codesign methodologyTommy King-Yin Cheung, Graham R. Hellestrand, Prasert Kanthamanon. 299-305 [doi]
• Non-scan design for testable data paths using thru operationKatsuyuki Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo Fujiwara. 313-318 [doi]
• Block-level fault isolation using partition theory and logic minimization techniquesC.-J. Richard Shi. 319-324 [doi]
• Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test systemKatsuyoshi Miura, Koji Nakamae, Hiromu Fujioka. 329-332 [doi]
• Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elementsWenming Zhou, Zeyi Wang, Lan Rao. 339-343 [doi]
• Simulation of gate switching characteristics of a miniaturized MOSFET based on a non-isothermal non-equilibrium transport modelWon-Cheol Choi, Hirobumi Kawashima, Ryo Dang. 345-348 [doi]
• Multi-project chip activities in Korea-IDEC perspectiveChong-Min Kyung, In-Cheol Park, Ho-Jun Song. 353-357 [doi]
• Multi-project chip service for university and industry in TaiwanJen-Sheng Hwang. 359-363 [doi]
• A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interfaceYoshiyuki Ito, Yuichi Nakamura. 377-382 [doi]
• VIDE: a visual VHDL integrated design environmentJinian Bian, Hongxi Xue, Ming Su. 383-386 [doi]
• Advanced processor design using hardware description language AIDLTakayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku, Kisaburo Nakazawa. 387-390 [doi]
• Adaptive models for input data compaction for power simulatorsRadu Marculescu, Diana Marculescu, Massoud Pedram. 391-396 [doi]
• Fuzzy-based circuit partitioning in built-in current testingWang-Dauh Tseng, Kuochen Wang. 397-400 [doi]
• Modeling and detection of dynamic errors due to reflection- and crosstalk-noiseJürgen Schrage. 405-408 [doi]
• Low-power multiple-valued current-mode integrated circuit with current-source control and its applicationTakahiro Hanyu, Satoshi Kazama, Michitaka Kameyama. 413-418 [doi]
• Optimal loop bandwidth design for low noise PLL applicationsKyoo Hyun Lim, Seung Hee Choi, Beomsup Kim. 425-428 [doi]
• Collaboration between university and industryTokinori Kozawa. 433 [doi]
• ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applicationsMin Xu, Fadi J. Kurdahi. 435-440 [doi]
• Bit-serial pipeline synthesis and layout for large-scale configurable systemsTsuyoshi Isshiki, Wayne Wei-Ming Dai, Hiroaki Kunieda. 441-446 [doi]
• AQUILA: An equivalence verifier for large sequential circuitsShi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen. 455-460 [doi]
• On the representational power of bit-level and word-level decision diagramsBernd Becker, Rolf Drechsler, Reinhard Enders. 461-467 [doi]
• Learning heuristics for OKFDD minimization by evolutionary algorithmsNicole Göckel, Rolf Drechsler, Bernd Becker. 469-472 [doi]
• On properties of Kleene TDDsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. 473-476 [doi]
• A time-domain method for numerical noise analysis of oscillatorsMakiko Okumura, Hiroshi Tanimoto. 477-482 [doi]
• A new linear-time harmonic balance algorithm for cyclostationary noise analysis in RF circuitsJaijeet S. Roychowdhury, Peter Feldmann. 483-492 [doi]
• Enhancement of parallelism for tearing-based circuit simulationKoutaro Hachiya, Toshiyuki Saito, Toshiyuki Nakata, Norio Tanabe. 493-498 [doi]
• Processor-core based design and testPeter Marwedel. 499-502 [doi]
• Architecture evaluation based on the datapath structure and parallel constraintMasayuki Yamaguchi, Akihisa Yamada, Toshihiro Nakaoka, Takashi Kambe. 503-508 [doi]
• A constructive method for data path area estimation during high-level VLSI synthesisNatesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri. 509-515 [doi]
• Statistical design of macro-models for RT-level power evaluationQing Wu, Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram. 523-528 [doi]
• AND/OR reasoning graphs for determining prime implicants in multi-level combinational networksDominik Stoffel, Wolfgang Kunz, Stefan Gerber. 529-538 [doi]
• Efficient synthesis of AND/XOR networksYibin Ye, Kaushik Roy. 539-544 [doi]
• An optimization of AND-OR-EXOR three-level networksDebatosh Debnath, Tsutomu Sasao. 545-550 [doi]
• A new description of CMOS circuits at switch-levelMassoud Pedram, Xunwei Wu. 551-556 [doi]
• A two-dimensional transistor placement for cell synthesisShunji Saika, Masahiro Fukui, Noriko Shinomiya, Toshiro Akino. 557-562 [doi]
• DP-Gen: a datapath generator for multiple-FPGA applicationsWen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-chin Lin. 563-568 [doi]
• A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAsNozomu Togawa, Masao Sato, Tatsuo Ohtsuki. 569-578 [doi]
• Not necessarily more switches more routability [sic.]Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama. 579-584 [doi]
• On the control-subroutine implementation of subprogram synthesisCheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee. 587-592 [doi]
• A procedure for software synthesis from VHDL modelsVenkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee. 593-598 [doi]
• Built-in chaining: introducing complex components into architectural synthesisPeter Marwedel, Birger Landwehr, Rainer Dömer. 599-605 [doi]
• Cube-embedding based state encoding for low power designDe-Sheng Chen, Majid Sarrafzadeh. 613-618 [doi]
• A mapping from sequence-pair to rectangular dissectionHiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani. 625-633 [doi]
• Solving constrained via minimization by compact linear programmingC.-J. Richard Shi. 635-640 [doi]
• Efficient routability checking for global wires in planar layoutsNaoyuki Iso, Yasushi Kawaguchi, Tomio Hirata. 641-644 [doi]
• Topological routing path search algorithm with incremental routability testToshiyuki Hama, Hiroaki Etoh. 645-648 [doi]
• HK386: an x86-compatible 32-bit CISC microprocessorChong-Min Kyung, In-Cheol Park, Se-Kyoung Hong, K. S. Seong, B. S. Kong, S. J. Lee, Hoon Choi, S. R. Maeng, D. T. Kim, Jong-Sun Kim, S. H. Park, Y. J. Kang. 661-662 [doi]
• Super low power 8-bit CPU with pass-transistor logicKazuo Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi. 663-664 [doi]
• A functional memory type parallel processor for vector quantizationKazutoshi Kobayashi, Masayoshi Kinoshita, M. Takeuchi, Hidetoshi Onodera, Keikichi Tamaru. 665-666 [doi]
• High speed bit-serial parallel processing on array architectureKazuhito Ito, Takenobu Shimizugashira, Hiroaki Kunieda. 667-668 [doi]
• Self-timed 1-D ICT processorTin-Chak Johnson Pang, Oliver Chiu-sing Choy, Cheong-fat Chan, Wai-kuen Cham. 669-670 [doi]
• A real-time high performance edge detector for computer vision applicationsFahad M. Alzahrani, Tom Chen. 671-672 [doi]
• An LSI implementation of the simple serial synchronized multistage interconnection networkTakayuki Kamei, Masashi Sasahara, Hideharu Amano. 673-674 [doi]
• The RDT network router chipHiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh. 675-676 [doi]
• Single cycle access cache for the misaligned data and instruction prefetchJoon-Seo Yim, Hee Choul Lee, Tae Hoon Kim, Bong-Il Park, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung. 677-678 [doi]
• VLSI implementation of a real-time operating systemTakumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai. 679-680 [doi]
• A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 psYong-Bin Kim, Tom Chen. 681-682 [doi]
• A current mode cyclic A/D converter with a 0.8 μm CMOS processMasaki Kondo, Hidetoshi Onodera, Keikichi Tamaru. 683-684 [doi]
• A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuitYasuhiro Sugimoto, Tetsuya Iida. 685-686 [doi]