Abstract is missing.
- Analog circuit verification by statistical model checkingYing-Chih Wang, Anvesh Komuravelli, Paolo Zuliani, Edmund M. Clarke. 1-6 [doi]
- FSM model abstraction for analog/mixed-signal circuits by learning from I/O trajectoriesChenjie Gu, Jaijeet S. Roychowdhury. 7-12 [doi]
- A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platformsXuexin Liu, Hao Yu, Jacob Relles, Sheldon X.-D. Tan. 13-18 [doi]
- Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stampsHui Xu, Guoyong Shi, Xiaopeng Li. 19-24 [doi]
- Geometry variations analysis of TiO2 thin-film and spintronic memristorsMiao Hu, Hai Li, Yiran Chen, XiaoBin Wang, Robinson E. Pino. 25-30 [doi]
- AdaMS: Adaptive MLC/SLC phase-change memory design for file storageXiangyu Dong, Yuan Xie. 31-36 [doi]
- System accuracy estimation of SRAM-based device authenticationJoonsoo Kim, Joonsoo Lee, Jacob A. Abraham. 37-42 [doi]
- On-chip hybrid power supply system for wireless sensor nodesWulong Liu, Yu Wang 0002, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang. 43-48 [doi]
- A moment-matching scheme for the passivity-preserving model order reduction of indefinite descriptor systems with possible polynomial partsZheng Zhang, Qing Wang, Ngai Wong, Luca Daniel. 49-54 [doi]
- Balanced truncation for time-delay systems via approximate GramiansXiang Wang, Qing Wang, Zheng Zhang, Quan Chen, Ngai Wong. 55-60 [doi]
- Efficient sensitivity-based capacitance modeling for systematic and random geometric variationsYu Bi, P. Harpe, N. P. van der Meijs. 61-66 [doi]
- Parallel statistical capacitance extraction of on-chip interconnects with an improved geometric variation modelWenjian Yu, Chao Hu, Wangyang Zhang. 67-72 [doi]
- A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable videoCheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng. 73-74 [doi]
- A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOSBenjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. 75-76 [doi]
- A 4.32 mm:::2::: 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applicationsDan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiaoyang Zeng. 77-78 [doi]
- All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counterJaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada. 79-80 [doi]
- Jitter amplifier for oscillator-based true random number generatorTakehiko Amaki, Masanori Hashimoto, Takao Onoye. 81-82 [doi]
- A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particlesJun Furuta, C. Hamanaka, K. Kobayashi, Hidetoshi Onodera. 83-84 [doi]
- Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanismYu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo. 85-86 [doi]
- Geyser-2: The second prototype CPU with fine-grained run-time power gatingLei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo. 87-88 [doi]
- An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architectureYoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama. 89-90 [doi]
- Design and chip implementation of a heterogeneous multi-core DSPShuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen. 91-92 [doi]
- A low-power management technique for high-performance domino circuitsYu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo. 93-94 [doi]
- Design and evaluation of variable stages pipeline processor chipTomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo. 95-96 [doi]
- TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profilerShuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung. 97-98 [doi]
- Design and implementation of a high performance closed-loop MIMO communications with ultra low complexity handsetYu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma. 99-100 [doi]
- A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection techniqueAhmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa. 101-102 [doi]
- An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generationWei Deng, Kenichi Okada, Akira Matsuzawa. 103-104 [doi]
- A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technologyYu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu. 105-106 [doi]
- A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOSNguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada. 107-108 [doi]
- An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOSXin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai. 109-110 [doi]
- Robust and efficient baseband receiver design for MB-OFDM UWB systemWen Fan, Oliver Chiu-sing Choy. 111-112 [doi]
- A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladderYuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa. 113-114 [doi]
- A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning systemTing Gao, Wei Li, Ning Li, Junyan Ren. 115-116 [doi]
- An adaptively biased low-dropout regulator with transient enhancementChenchang Zhan, Wing-Hung Ki. 117-118 [doi]
- A low-power triple-mode sigma-delta DAC for reconfigurable (WCDMA/TD-SCDMA/GSM) transmittersDong Qiu, Ting Yi, Zhiliang Hong. 119-120 [doi]
- A simple non-coherent solution to the UWB-IR communicationMohiuddin Hafiz, Nobuo Sasaki, Kentaro Kimoto, Takamaro Kikkawa. 121-122 [doi]
- Thermally optimal stop-go scheduling of task graphs with real-time constraintsPratyush Kumar, Lothar Thiele. 123-128 [doi]
- Register allocation for write activity minimization on non-volatile main memoryYazhi Huang, Tiantian Liu, Chun Jason Xue. 129-134 [doi]
- Leakage conscious DVS scheduling for peak temperature minimizationVivek Chaturvedi, Gang Quan. 135-140 [doi]
- Reconfiguration-aware real-time scheduling under QoS constraintHessam Kooti, Deepak Mishra, Eli Bozorgzadeh. 141-146 [doi]
- Template-based memory access engine for accelerators in SoCsBin Li, Zhen Fang, Ravi Iyer. 147-153 [doi]
- Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systemsAbdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch. 154-159 [doi]
- Network-on-Chip router design with Buffer-StealingWan-Ting Su, Jih-Sheng Shen, Pao-Ann Hsiung. 160-164 [doi]
- Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graphTae-ho Shin, Hyunok Oh, Soonhoi Ha. 165-170 [doi]
- A fast approximation technique for power grid analysisMysore Sriram. 171-175 [doi]
- Equivalent lumped element models for various n-port Through Silicon Vias networksKhaled Salah, Hani Ragai, Yehea I. Ismail, Alaa El Rouby. 176-183 [doi]
- Clock tree optimization for Electromagnetic Compatibility (EMC)Xuchu Hu, Matthew R. Guthaus. 184-189 [doi]
- Pulser gating: A clock gating of pulsed-latch circuitsSangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin. 190-195 [doi]
- Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-ICMeng-Fan Chang, Pi-Feng Chiu, Shyh-Shyuan Sheu. 197-203 [doi]
- Emerging sensing techniques for emerging memoriesYiran Chen, Hai Li. 204-210 [doi]
- A frequent-value based PRAM memory architectureGuangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie. 211-216 [doi]
- Two-terminal resistive switches (memristors) for memory and logic applicationsWei Lu, Kuk-Hwan Kim, Ting Chang, Siddharth Gaba. 217-223 [doi]
- Co-design of cyber-physical systems via controllers with flexible delay constraintsDip Goswami, Reinhard Schneider, Samarjit Chakraborty. 225-230 [doi]
- Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary TranslationAng-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang. 231-236 [doi]
- Fast hybrid simulation for accurate decoded video quality assessment on MPSoC platforms with resource constraintsDeepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann. 237-242 [doi]
- On the interplay of loop caching, code compression, and cache configurationMarisha Rawlins, Ann Gordon-Ross. 243-248 [doi]
- Path criticality computation in parameterized statistical timing analysisJaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham. 249-254 [doi]
- Run-time adaptable on-chip thermal triggersPratyush Kumar, David Atienza. 255-260 [doi]
- Rethinking thermal via planning with timing-power-temperature dependence for 3D ICsKan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong. 261-266 [doi]
- The impact of inverse narrow width effect on sub-threshold device sizingJun Zhou, Senthil Jayapal, Jan Stuyt, Jos Huisken, Harmke de Groot. 267-272 [doi]
- Post-silicon bug detection for variation induced electrical bugsMing Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng. 273-278 [doi]
- Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designsJing-Jia Liou, Ying-Yen Chen, Chun-Chia Chen, Chung-Yen Chien, Kuo-Li Wu. 279-284 [doi]
- Run-time adaptive performance compensation using on-chip sensorsMasanori Hashimoto. 285-290 [doi]
- The alarms project: A hardware/software approach to addressing parameter variationsDavid Brooks. 291 [doi]
- Automatic formal verification of reconfigurable DSPsMiroslav N. Velev, Ping Gao 0002. 293-296 [doi]
- SoC HW/SW verification and validationChung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang, Ting-Mao Chang. 297-300 [doi]
- Utilizing high level design information to speed up post-silicon debuggingMasahiro Fujita. 301-305 [doi]
- From RTL to silicon: The case for automated debugAndreas G. Veneris, Brian Keng, Sean Safarpour. 306-310 [doi]
- Multi-core parallel simulation of System-level Description LanguagesRainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer. 311-316 [doi]
- Variation-aware logic mapping for crossbar nano-architecturesMasoud Zamani, Mehdi Baradaran Tahoori. 317-322 [doi]
- Routing with graphene nanoribbonsTan Yan, Qiang Ma 0002, Scott Chilstedt, Martin D. F. Wong, Deming Chen. 323-329 [doi]
- ILP-based inter-die routing for 3D ICsChia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu. 330-335 [doi]
- CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuitsShashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli. 336-343 [doi]
- OPAL: A multi-layer hybrid photonic NoC for 3D ICsSudeep Pasricha, Shirish Bahirat. 345-350 [doi]
- Enabling quality-of-service in nanophotonic network-on-chipJin Ouyang, Yuan Xie. 351-356 [doi]
- Vertical interconnects squeezing in symmetric 3D mesh Network-on-ChipCheng Liu, Lei Zhang 0008, Yinhe Han, Xiaowei Li. 357-362 [doi]
- Power-efficient tree-based multicast support for Networks-on-ChipWenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu. 363-368 [doi]
- Area-efficient FPGA logic elements: Architecture and synthesisJason Helge Anderson, Qiang Wang. 369-375 [doi]
- Selectively patterned masks: Structured ASIC with asymptotically ASIC performanceDonkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin. 376-381 [doi]
- A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimizationShao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang. 382-387 [doi]
- SETmap: A soft error tolerant mapping algorithm for FPGA designs with low powerChi-Chen Peng, Chen Dong, Deming Chen. 388-393 [doi]
- Future electron-beam lithography and implications on design and CAD toolsJack J. H. Chen, Faruk Krecinic, Jen-Hom Chen, Raymond P. S. Chen, Burn J. Lin. 403-404 [doi]
- Exploration of VLSI CAD researches for early design rule evaluationChul-Hong Park, David Z. Pan, Kevin Lucas. 405-406 [doi]
- Handling dynamic frequency changes in statically scheduled cycle-accurate simulationMarius Gligor, Frédéric Pétrot. 407-412 [doi]
- Coarse-grained simulation method for performance evaluation a of shared memory systemRyo Kawahara, Kenta Nakamura, Kouichi Ono, Takeo Nakada, Yoshifumi Sakamoto. 413-418 [doi]
- T-SPaCS - A two-level single-pass cache simulation methodologyWei Zang, Ann Gordon-Ross. 419-424 [doi]
- Fast data-cache modeling for native co-simulationHector Posadas, Luis Diaz, Eugenio Villar. 425-430 [doi]
- On the design and analysis of fault tolerant NoC architecture using spare routersYung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu. 431-436 [doi]
- A resilient on-chip router design through data path salvagingCheng Liu, Lei Zhang 0008, Yinhe Han, Xiaowei Li. 437-442 [doi]
- NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faultsSudeep Pasricha, Yong Zou. 443-448 [doi]
- A thermal-aware application specific routing algorithm for Network-on-Chip designZhiliang Qian, Chi-Ying Tsui. 449-454 [doi]
- An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuitsYu Pang, Katarzyna Radecka, Zeljko Zilic. 455-460 [doi]
- Register pressure aware scheduling for high level synthesisRami Beidas, Wai Sum Mong, Jianwen Zhu. 461-466 [doi]
- Parallel cross-layer optimization of high-level synthesis and physical designJames Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng. 467-472 [doi]
- Network flow-based simultaneous retiming and slack budgeting for low power designBei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto. 473-478 [doi]
- Managing complexity in design debugging with sequential abstraction and refinementBrian Keng, Andreas G. Veneris. 479-484 [doi]
- Facilitating unreachable code diagnosis and debuggingHong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo. 485-490 [doi]
- Deterministic test for the reproduction and detection of board-level functional failuresHongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty. 491-496 [doi]
- Equivalence checking of scheduling with speculative code transformations in high-level synthesisChi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou. 497-502 [doi]
- An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designsKyoung-Hwan Lim, Taewhan Kim. 503-508 [doi]
- On applying erroneous clock gating conditions to further cut down powerTak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu. 509-514 [doi]
- Low power discrete voltage assignment under clock skew schedulingLi Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng. 515-520 [doi]
- A practical method for multi-domain clock skew optimizationYanling Zhi, Hai Zhou, Xuan Zeng. 521-526 [doi]
- Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree constructionJia-Ru Chuang, Jai-Ming Lin. 527-532 [doi]
- Cut-demand based routing resource allocation and consolidation for routability enhancementFong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak. 533-538 [doi]
- Negotiation-based layer assignment for via count and via overflow minimizationWen-Hao Liu, Yih-Lang Li. 539-544 [doi]
- Wire synthesizable global routing for timing closureMichael D. Moffitt, Chin-Ngai Sze. 545-550 [doi]
- Biological information sensing technologies for medical, health care, and wellness applicationsMasaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato. 551-555 [doi]
- Ultra-low power microcontrollers for portable, wearable, and implantable medical electronicsSrinivasa R. Sridhara. 556-560 [doi]
- Human++: Wireless autonomous sensor technology for body area networksValer Pop, Ruben de Francisco, H. Pflug, J. Santana, H. Visser, Ruud J. M. Vullers, Harmke de Groot, Bert Gyselinckx. 561-566 [doi]
- Healthcare of an organization: Using wearable sensors and feedback system for energizing workersKoji Ara, Tomoaki Akitomi, Nobuo Sato, Satomi Tsuji, Miki Hayakawa, Yoshihiro Wakisaka, Norio Ohkubo, Rieko Otsuka, Fumiko Beniyama, Norihiko Moriwaki, Kazuo Yano. 567-572 [doi]
- A polynomial-time custom instruction identification algorithm based on dynamic programmingJunwhan Ahn, Imyong Lee, Kiyoung Choi. 573-578 [doi]
- Exploring the fidelity-efficiency design space using imprecise arithmeticJiawei Huang, John Lach. 579-584 [doi]
- Throughput optimization for latency-insensitive system with minimal queue insertionJuinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho. 585-590 [doi]
- A fast and effective dynamic trace-based method for analyzing architectural performanceYi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang. 591-596 [doi]
- Controlling NBTI degradation during static burn-in testingAshutosh Chakraborty, David Z. Pan. 597-602 [doi]
- A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designsYongho Lee, Taewhan Kim. 603-608 [doi]
- NBTI-aware power gating designMing-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, Shih-Chieh Chang. 609-614 [doi]
- Robust power gating reactivation by dynamic wakeup sequence throttlingTung-Yeh Wu, Shih-Hsin Hu, Jacob A. Abraham. 615-620 [doi]
- Robust Clock Tree Synthesis with timing yield optimization for 3D-ICsJae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan. 621-626 [doi]
- Track routing optimizing timing and yieldX. Gao, L. Macchiarlo. 627-632 [doi]
- Simultaneous redundant via insertion and line end extension for yield optimizationShing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao. 633-638 [doi]
- Pruning-based trace signal selection algorithmKang Zhao, Jinian Bian. 639-644 [doi]
- Temporal and spatial isolation in a virtualization layer for multi-core processor based information appliancesTatsuo Nakajima, Yuki Kinebuchi, Hiromasa Shimada, Alexandre Courbot, Tsung-Han Lin. 645-652 [doi]
- Mathematical limits of parallel computation for embedded systemsJason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden. 653-660 [doi]
- An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAsJen-Wei Hsieh, Yuan-Hao Chang, Wei-Li Lee. 661-667 [doi]
- Power management strategies in data transmissionTiefei Zhang, Ying-Jheng Chen, Che-Wei Chang, Chuan-Yue Yang, Tei-Wei Kuo, Tianzhou Chen. 668-675 [doi]
- Robust spatial correlation extraction with limited sample via L1-norm penaltyMingzhi Gao, Zuochang Ye, Dajie Zeng, Yan Wang, Zhiping Yu. 677-682 [doi]
- Device-parameter estimation with on-chip variation sensors considering random variabilityKenichi Shinkai, Masanori Hashimoto. 683-688 [doi]
- Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliabilityJianxin Fang, Sachin S. Sapatnekar. 689-694 [doi]
- Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displaysChih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy. 695-700 [doi]
- A physical-location-aware fault redistribution for maximum IR-drop reductionFu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang. 701-706 [doi]
- On the impact of gate oxide degradation on SRAM dynamic and static write-abilityVikas Chandra, Robert C. Aitken. 707-712 [doi]
- A self-testing and calibration method for embedded successive approximation register ADCXuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu. 713-718 [doi]
- On-chip dynamic signal sequence slicing for efficient post-silicon debuggingYeonbok Lee, Takeshi Matsumoto, Masahiro Fujita. 719-724 [doi]
- AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processorsAbhishek A. Sinkar, Nam Sung Kim. 725-730 [doi]
- Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systemsJunhe Gan, Flavius Gruian, Paul Pop, Jan Madsen. 731-736 [doi]
- Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systemsJingqing Mu, Roman L. Lysecky. 737-742 [doi]
- Battery-aware task scheduling in distributed mobile systems with lifetime constraintJiayin Li, Meikang Qiu, Jianwei Niu, Tianzhou Chen. 743-748 [doi]
- Advanced system LSIs for home 3D systemTakao Suzuki. 749-754 [doi]
- Development of low power and high performance application processor (T6G) for multimedia mobile applicationsYoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki. 755-759 [doi]
- Design constraint of fine grain supply voltage control LSIAtsuki Inoue. 760-765 [doi]
- FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC designMasaru Takahashi. 766-769 [doi]
- An RTL-to-GDS2 design methodology for advanced system LSINobuyuki Nishiguchi. 770-774 [doi]
- High performance lithographic hotspot detection using hierarchically refined machine learningDuo Ding, Andres J. Torres, Fedor G. Pikus, David Z. Pan. 775-780 [doi]
- Rapid layout pattern classificationJen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska. 781-786 [doi]
- Mask cost reduction with circuit performance consideration for self-aligned double patterningHongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao. 787-792 [doi]
- Post-routing layer assignment for double patterningJian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng. 793-798 [doi]
- Fault simulation and test generation for clock delay faultsYoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja. 799-805 [doi]
- Compression-aware capture power reduction for at-speed testingJia Li, Qiang Xu, Dong Xiang. 806-811 [doi]
- Fault diagnosis aware ATE assisted test response compactionJ. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker. 812-817 [doi]
- Secure scan design using shift register equivalents against differential behavior attackHideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto. 818-823 [doi]
- An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designsKuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho. 825-830 [doi]
- An integer programming placement approach to FPGA clock power reductionAlireza Rakhshanfar, Jason Helge Anderson. 831-836 [doi]
- Row-based area-array I/O design planning in concurrent chip-package design flowRen-Jie Lee, Hung-Ming Chen. 837-842 [doi]
- A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routingQiang Ma 0002, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young. 843-848 [doi]