Table of Contents

• Engineering complex systems for health, security and the environmentGiovanni De Micheli. 1-6 [doi]
• Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issuesVijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman. 7-16 [doi]
• JOP-plus - A processor for efficient execution of java programs extended with GALS concurrencyMuhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic. 17-22 [doi]
• An application classification guided cache tuning heuristic for multi-core architecturesMarisha Rawlins, Ann Gordon-Ross. 23-28 [doi]
• Security Enhanced Linux on embedded systems: A hardware-accelerated implementationLeandro Fiorin, Alberto Ferrante, Konstantinos Padarnitsas, Francesco Regazzoni. 29-34 [doi]
• PRR: A low-overhead cache replacement algorithm for embedded processorsWei-Che Tseng, Chun Jason Xue, Qingfeng Zhuge, Jingtong Hu, Edwin Hsing-Mean Sha. 35-40 [doi]
• Incremental power network analysis using backward random walksBaktash Boghrati, Sachin S. Sapatnekar. 41-46 [doi]
• Thermal-aware power network design for IR drop reduction in 3D ICsZuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang 0002, Tingting Huang, Yuan Xie. 47-52 [doi]
• The feasibility of Carbon Nanotubes for power delivery in 3-D Integrated CircuitsNauman H. Khan, Soha Hassoun. 53-58 [doi]
• An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designsYi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao. 59-65 [doi]
• An ILP-based obstacle-avoiding routing algorithm for pin-constrained EWOD chipsJia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho. 67-72 [doi]
• A Look Up Table design with 3D bipolar RRAMsYi-Chung Chen, Wei Zhang, Hai Li. 73-78 [doi]
• Low power memristor-based ReRAM design with Error Correcting CodeDimin Niu, Yang Xiao, Yuan Xie. 79-84 [doi]
• Synthesis of reversible circuits with minimal lines for large functionsMathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler. 85-92 [doi]
• Accelerated processing and the Fusion System ArchitectureMike O'Connor. 93 [doi]
• Platform characterization for Domain-Specific ComputingAlex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou. 94-99 [doi]
• GreenDroid: An architecture for the Dark Silicon AgeNathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng, Vikram Bhatt, Joe Auricchio, Steven Swanson, Michael Bedford Taylor. 100-105 [doi]
• Accelerator-rich architectures: Implications, opportunities and challengesRavi Iyer. 106-107 [doi]
• A reconfigurable platform for the design and verification of domain-specific acceleratorsSungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan. 108-113 [doi]
• Learning-based power management for multi-core processors via idle period manipulationRong Ye, Qiang Xu. 115-120 [doi]
• Memory access aware power gating for MPSoCsYe-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang. 121-126 [doi]
• Buffer minimization in pipelined SDF scheduling on multi-core platformsYuankai Chen, Hai Zhou. 127-132 [doi]
• A hierarchical C2RTL framework for FIFO-connected stream applicationsShuangchen Li, Yongpan Liu, Daming Zhang, Xinyu He, Pei Zhang, Huazhong Yang. 133-138 [doi]
• Escape routing of differential pairs considering length matchingTai-Hung Li, Wan-Chun Chen, Xian-Ting Cai, Tai-Chen Chen. 139-144 [doi]
• An any-angle routing method using quasi-Newton methodYukihide Kohira, Atsushi Takahashi. 145-150 [doi]
• Linear optimal one-sided single-detour algorithm for untangling twisted busTao Lin, Sheqin Dong, Song Chen, Satoshi Goto. 151-156 [doi]
• LEMAR: A novel length matching routing algorithm for analog and mixed signal circuitsHailong Yao, Yici Cai, Qiang Gao. 157-162 [doi]
• An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technologyChia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra. 163-168 [doi]
• CODA: A concurrent online delay measurement architecture for critical pathsYubin Zhang, Haile Yu, Qiang Xu. 169-174 [doi]
• Low-cost control flow error protection by exploiting available redundancies in the pipelineMohammad Abdur Rouf, Soontae Kim. 175-180 [doi]
• Detection and diagnosis of faulty quantum circuitsAlexandru Paler, Ilia Polian, John P. Hayes. 181-186 [doi]
• Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCsSascha Roloff, Frank Hannig, Jürgen Teich. 187-192 [doi]
• Invasive manycore architecturesJörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe. 193-200 [doi]
• Hardware prototyping of novel invasive multicore architecturesJürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf König, David May. 201-206 [doi]
• Invasive Computing for robotic visionJohny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Rüdiger Dillmann. 207-212 [doi]
• Abstract system-level models for early performance and power explorationAndreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, Parisa Razaghi. 213-218 [doi]
• Virtual prototyping of Cyber-Physical SystemsWolfgang Müller 0003, Markus Becker, Ahmed Elfeky, Anthony DiPasquale. 219-226 [doi]
• Parallel discrete event simulation of Transaction Level ModelsRainer Dömer, Weiwei Chen, Xu Han. 227-231 [doi]
• Post-silicon patching for verification/debugging with high-level models and programmable logicMasahiro Fujita, Hiroaki Yoshida. 232-237 [doi]
• Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency rangeKeisuke Inoue, Mineo Kaneko. 239-244 [doi]
• Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuitsWen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng. 245-250 [doi]
• Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesisYuko Hara, Hiroyuki Tomiyama. 251-256 [doi]
• An integrated and automated memory optimization flow for FPGA behavioral synthesisYuxin Wang, Peng Zhang, Xu Cheng, Jason Cong. 257-262 [doi]
• EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulationDuo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan. 263-270 [doi]
• GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigationSaket Gupta, Sachin S. Sapatnekar. 271-276 [doi]
• Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICsKwanyeob Chae, Saibal Mukhopadhyay. 277-282 [doi]
• Body bias clustering for low test-cost post-silicon tuningShuta Kimura, Masanori Hashimoto, Takao Onoye. 283-289 [doi]
• Bug localization techniques for effective post-silicon validationSubhasish Mitra, David Lin, Nagib Hakim, Donald S. Gardner. 291 [doi]
• Improving validation coverage metrics to account for limited observabilityPeter Lisherness, Kwang-Ting Cheng. 292-297 [doi]
• Automated data analysis techniques for a modern silicon debug environmentYu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita. 298-303 [doi]
• Optimizing test-generation to the execution platformAmir Nahir, Avi Ziv, Subrat Panda. 304-309 [doi]
• When to forget: A system-level perspective on STT-RAMsKarthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan. 311-316 [doi]
• Write-activity-aware page table management for PCM-based embedded systemsTianzheng Wang, Duo Liu, Zili Shao, Chengmo Yang. 317-322 [doi]
• Probabilistic design in spintronic memory and logic circuitYiran Chen, Yaojun Zhang, Peiyuan Wang. 323-328 [doi]
• Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) deviceMeng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen, Hiroyuki Yamauchi, Pi-Feng Chiu, Shyh-Shyuan Sheu. 329-334 [doi]
• Block-level 3D IC design with through-silicon-via planningDae-Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim. 335-340 [doi]
• Micro-bump assignment for 3D ICs using order relationTa-Yu Kuan, Yi-Chun Chang, Tai-Chen Chen. 341-346 [doi]
• Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICsXin Zhao, Sung Kyu Lim. 347-352 [doi]
• Parallel implementation of R-trees on the GPULijuan Luo, Martin D. F. Wong, Lance Leong. 353-358 [doi]
• An adaptive LU factorization algorithm for parallel circuit simulationXiaoming Chen, Yu Wang 0002, Huazhong Yang. 359-364 [doi]
• Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuitsHiroki Kurobe, Tadatoshi Sekine, Hideki Asai. 365-370 [doi]
• Crosstalk-aware statistical interconnect delay calculationQin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs. 371-376 [doi]
• Fast floating random walk algorithm formulti-dielectric capacitance extraction with numerical characterization of Green's functionsHao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye. 377-382 [doi]
• Challenges and opportunities of internet of thingsYen-Kuang Chen. 383-388 [doi]
• Application specific sensor node architecture optimization - Experiences from field deploymentsWei Liu, Xiaotian Fei, Tao Tang, Pengjun Wang, Hong Luo, Beixing Deng, Huazhong Yang. 389-394 [doi]
• System-wide profiling and optimization with virtual machinesShih-Hao Hung, Tei-Wei Kuo, Chi-Sheng Shih, Chia-Heng Tu. 395-400 [doi]
• Power optimization of wireless video sensor nodes in M2M networksShao-Yi Chien, Teng-Yuan Cheng, Chieh-Chuan Chiu, Pei-Kuei Tsung, Chia-han Lee, V. Srinivasa Somayazulu, Yen-Kuang Chen. 401-405 [doi]
• A multi-Vdd dynamic variable-pipeline on-chip router for CMPsHiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. 407-412 [doi]
• ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architecturesAmir-Mohammad Rahmani, Khalid Latif 0002, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 413-418 [doi]
• Memory-aware mapping and scheduling of tasks and communications on many-core SoCJinho Lee, Kiyoung Choi. 419-424 [doi]
• A fast thermal aware placement with accurate thermal analysis based on Green functionSuradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen. 425-430 [doi]
• Crosstalk-aware power optimization with multi-bit flip-flopsChih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin. 431-436 [doi]
• Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimizationYen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li. 437-442 [doi]
• Voltage island-driven floorplanning considering level shifter placementJai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu. 443-448 [doi]
• Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systemsDukyoung Yun, Sungchan Kim, Soonhoi Ha. 449-454 [doi]
• Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUsRohit Sinha, Aayush Prakash, Hiren D. Patel. 455-460 [doi]
• An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolationWeiwei Chen, Rainer Dömer. 461-466 [doi]
• A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOSRyo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada, Akira Matsuzawa. 467-468 [doi]
• A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvesterPo-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai. 469-470 [doi]
• CMA-2 : The second prototype of a low power reconfigurable acceleratorMai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura. 471-472 [doi]
• Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applicationsShyang-Chyun Chen, Chao Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh. 473-474 [doi]
• Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading schemeShoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu. 475-476 [doi]
• Energy-efficient RISC design with on-demand circuit-level timing speculationTay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu. 477-478 [doi]
• A 60mW baseband SoC for CMMB receiverChuan Wu, Jialin Cao, Dan Bao, Yun Chen, Xiaoyang Zeng. 479-480 [doi]
• Proximity-Aware cache ReplicationChongmin Li, Dongsheng Wang, Haixia Wang, Yibo Xue, Jian Li. 481-486 [doi]
• Dynamic reusability-based replication with network address mapping in CMPsJinglei Wang, Dongsheng Wang, Haixia Wang, Yibo Xue. 487-492 [doi]
• Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoCKe Yue, Frank Lockom, Zheng Li, Soumia Ghalim, Shangping Ren, Lei Zhang 0008, Xiaowei Li 0001. 493-498 [doi]
• Using link-level latency analysis for path selection for real-time communication on NoCsHany Kashif, Hiren D. Patel, Sebastian Fischmeister. 499-504 [doi]
• A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraintsShihheng Tsai, Man-Yu Li, Chung-Yang Huang. 505-510 [doi]
• ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cellsXing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu. 511-516 [doi]
• Clock rescheduling for timing engineering change ordersKuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang. 517-522 [doi]
• Optimal prescribed-domain clock skew schedulingLi Li 0021, Yinghai Lu, Hai Zhou. 523-527 [doi]
• Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variablesYang Shang, Wei Fei, Hao Yu. 529-534 [doi]
• Time-domain performance bound analysis of analog circuits considering process variationsXuexin Liu, Sheldon X.-D. Tan, Zhigang Hao, Guoyong Shi. 535-540 [doi]
• Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free propertiesYang Song, Guoyong Shi. 541-546 [doi]
• Weakly nonlinear circuit analysis based on fast multidimensional inverse Laplace transformTingting Wang, Haotian Liu, Yuanzhe Wang, Ngai Wong. 547-552 [doi]
• A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOSKiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. 553-554 [doi]
• Simultaneous data and power transmission using nested clover coilsYasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda. 555-556 [doi]
• Complexity-effective auditory compensation with a controllable filter for digital hearing aidsYa-Ting Chang, Kuo-Chiang Chang, Yu-Ting Kuo, Chih-Wei Liu. 557-558 [doi]
• A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratiosAhmed Musa, Kenichi Okada, Akira Matsuzawa. 559-560 [doi]
• A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOSTakeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera. 561-562 [doi]
• A PVT-robust feedback class-C VCO using an oscillation swing enhancement techniqueWei Deng, Kenichi Okada, Akira Matsuzawa. 563-564 [doi]
• A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOSDan Bao, Xubin Chen, Yuebin Huang, Chuan Wu, Yun Chen, Xiaoyang Zeng. 565-566 [doi]
• Automatic timing granularity adjustment for host-compiled software simulationParisa Razaghi, Andreas Gerstlauer. 567-572 [doi]
• Performance estimation of embedded software with confidence levelsMarco Lattuada, Fabrizio Ferrandi. 573-578 [doi]
• Verifying dynamic power management schemes using statistical model checkingJayanand Asok Kumar, Shobha Vasudevan. 579-584 [doi]
• Formal methods for coverage analysis of architectural power states in power-managed designsAritra Hazra, Pallab Dasgupta, Ansuman Banerjee, Kevin Harer. 585-590 [doi]
• The impact of hot carriers on timing in large circuitsJianxin Fang, Sachin S. Sapatnekar. 591-596 [doi]
• A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessorsDa-Cheng Juan, Huapeng Zhou, Diana Marculescu, Xin Li. 597-602 [doi]
• On-chip statistical hot-spot estimation using mixed-mesh statistical polynomial expression generating and skew-normal based moment matching techniquesPei-Yu Huang, Yu-Min Lee, Chi-Wen Pan. 603-608 [doi]
• Design techniques for functional-unit power gating in the Ultra-Low-Voltage regionMichael B. Henry, Leyla Nazhandali. 609-614 [doi]
• Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systemsYan Zheng, Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani, Shiyuan Yang, Kwang-Ting Cheng. 615-620 [doi]
• GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexingDuo Ding, Bei Yu, David Z. Pan. 621-626 [doi]
• Charge replacement in hybrid electrical energy storage systemsQing Xie, Yanzhi Wang, Massoud Pedram, Younghyun Kim, Donghwa Shin, Naehyuck Chang. 627-632 [doi]
• Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessorsBorislav Alexandrov, Owen Sullivan, Satish Kumar, Saibal Mukhopadhyay. 633-638 [doi]
• Nano-Electro-Mechanical (NEM) relays and their application to FPGA routingChen Chen, W. Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Daesung Lee 0002, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra. 639 [doi]
• Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reductionTao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi. 640-645 [doi]
• Post silicon skew tuning: Survey and analysisMac Y. C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang. 646-651 [doi]
• Compilation and architecture support for customized vector instruction extensionJason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang 0001, Bin Liu 0006, Raghu Prabhakar, Glenn Reinman, Marco Vitanza. 652-657 [doi]
• Thread affinity mapping for irregular data access on shared Cache GPGPUHsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou. 659-664 [doi]
• Modular scheduling of distributed heterogeneous time-triggered automotive systemsMartin Lukasiewycz, Reinhard Schneider 0001, Dip Goswami, Samarjit Chakraborty. 665-670 [doi]
• RAISE: Reliability-Aware Instruction SchEduling for unreliable hardwareSemeen Rehman, Muhammad Shafique, Florian Kriebel, Jörg Henkel. 671-676 [doi]
• On-line leakage-aware energy minimization scheduling for hard real-time systemsHuang Huang, Ming Fan, Gang Quan. 677-682 [doi]
• A formal approach to debug polynomial datapath designsBijan Alizadeh. 683-688 [doi]
• Automated debugging of counterexamples in formal verification of pipelined microprocessorsMiroslav N. Velev, Ping Gao 0002. 689-694 [doi]
• On error tolerance and Engineering Change with Partially Programmable CircuitsHratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita. 695-700 [doi]
• On error modeling of electrical bugs for post-silicon timing validationMing Gao, Peter Lisherness, Kwang-Ting Cheng, Jing-Jia Liou. 701-706 [doi]
• Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded designYuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao. 707-712 [doi]
• Design-patterning co-optimization of SRAM robustness for double patterning lithographyVivek Joshi, Kanak Agarwal, Dennis Sylvester. 713-718 [doi]
• Efficient pattern relocation for EUV blank defect mitigationHongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit O. Topalaglu. 719-724 [doi]
• Character design and stamp algorithms for Character Projection Electron-Beam LithographyPeng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham. 725-730 [doi]
• Yield enhancement for 3D-stacked ICs: Recent advances and challengesQiang Xu, Li Jiang, Huiyun Li, Bill Eklow. 731-737 [doi]
• Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICsJing Xie, Yu Wang 0002, Yuan Xie. 738-743 [doi]
• On test and repair of 3D random access memoryCheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li. 744-749 [doi]
• Design for manufacturability and reliability for TSV-based 3D ICsDavid Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang. 750-755 [doi]
• The synthesis of linear Finite State Machine-based Stochastic Computational ElementsPeng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja. 757-762 [doi]
• Selective time borrowing for DSP pipelines with hybrid voltage control loopPaul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh. 763-768 [doi]
• EPROF: An energy/performance/reliability optimization framework for streaming applicationsYavuz Yetim, Sharad Malik, Margaret Martonosi. 769-774 [doi]
• BTI-aware design using variable latency unitsSaket Gupta, Sachin S. Sapatnekar. 775-780 [doi]
• Linear decomposition of index generation functionsTsutomu Sasao. 781-788 [doi]
• Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computationsOmid Sarbishei, Katarzyna Radecka. 789-794 [doi]
• Algorithm for synthesizing design context-aware fast carry-skip addersKiyoung Kim, Taewhan Kim. 795-800 [doi]
• A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoderHuailu Ren, Yibo Fan, Xinhua Chen, Xiaoyang Zeng. 801-806 [doi]
• Fine-grained dynamic voltage scaling on OLED displayXiang Chen, Jian Zheng, Yiran Chen, Wei Zhang, Hai Li. 807-812 [doi]
• A reconfigurable accelerator for neuromorphic object recognitionJagdish Sabarad, Srinidhi Kestur, Mi Sun Park, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla. 813-818 [doi]
• Efficient implementation of multi-moduli architectures for Binary-to-RNS conversionHéctor Pettenghi, Leonel Sousa, Jude Angelo Ambrose. 819-824 [doi]