Table of Contents

• On Generating High Quality Tests for Transition FaultsYun Shao, Irith Pomeranz, Sudhakar M. Reddy. 1 [doi]
• Exact Computation of Maximally Dominating Faults and Its Application to n-Detection TestsIlia Polian, Irith Pomeranz, Bernd Becker. 2-14 [doi]
• Maximum Distance TestingShiyi Xu, Jianwen Chen. 15 [doi]
• High Precision Result Evaluation of VLSIJunichi Hirase. 21-26 [doi]
• A Totally Self-Checking Dynamic Asynchronous DatapathJing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun. 27-32 [doi]
• Non-Intrusive Design of Concurrently Self-Testable FSMsPetros Drineas, Yiorgos Makris. 33 [doi]
• Test Limitations of Parametric Faults in Analog CircuitsJacob Savir, Zhen Guo. 39-44 [doi]
• Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication DevicesMasahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha. 45-48 [doi]
• On-chip Analog Response Extraction with 1-Bit ? - ModulatorsHao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu. 49 [doi]
• A State Reduction Method for Non-Scan Based FSM Testing with Don t Care Inputs Identification TechniqueToshinori Hosokawa, Hiroshi Date, Michiaki Muraoka. 55-60 [doi]
• Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test SequencesIrith Pomeranz, Sudhakar M. Reddy. 61-66 [doi]
• Test Data Compression Using Don?t-Care Identification and Statistical EncodingSeiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy. 67 [doi]
• Design for Two-Pattern Testability of Controller-Data Path CircuitsAtlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara. 73-79 [doi]
• MD-SCAN Method for Low Power Scan TestingTakaki Yoshida, Masafumi Watari. 80-85 [doi]
• Non-Scan Design for Testability Based on Fault Oriented Conflict AnalysisDong Xiang, Shan Gu, Hideo Fujiwara. 86 [doi]
• Specification and Design of a New Memory Fault SimulatorAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 92-97 [doi]
• DRAM Specific Approximation of the Faulty Behavior of Cell DefectsZaid Al-Ars, A. J. van de Goor. 98-103 [doi]
• An Access Timing Measurement Unit of Embedded MemoryShu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang. 104 [doi]
• A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan CircuitsIrith Pomeranz, Sudhakar M. Reddy. 110-115 [doi]
• Optimal Seed Generation for Delay Fault Detection BISTLihong Tong, Kazuki Suzuki, Hideo Ito. 116-121 [doi]
• On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data CommunicationsOctavian Petre, Hans G. Kerkhoff. 122 [doi]
• A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan DesignTomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara. 128-133 [doi]
• Test Requirement Analysis for Low Cost Hierarchical Test Path ConstructionYiorgos Makris, Alex Orailoglu. 134-139 [doi]
• Testable Realizations for ESOP Expressions of Logic FunctionsP. Zhongliang. 140 [doi]
• DPSC SRAM Transparent Test AlgorithmHong Sik Kim, Sungho Kang. 145-150 [doi]
• Tests for Word-Oriented Content Addressable MemoriesXuemei Zhao, Yizheng Yu, Chunxu Chen. 151-156 [doi]
• A High Performance IDDQ Testable Cache for Scaled CMOS TechnologiesSwarup Bhunia, Hai Li, Kaushik Roy. 157 [doi]
• Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect TopologyWichian Sirisaengtaksin, Sandeep K. Gupta. 163-169 [doi]
• A Testing Scheme for Crosstalk Faults Based on the Oscillation Test SignalMing Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen. 170-175 [doi]
• Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino CircuitsKazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita. 176-181 [doi]
• A Concurrent Fault Simulation for Crosstalk Faults in Sequential CircuitsMarong Phadoongsidhi, Kim T. Le, Kewal K. Saluja. 182 [doi]
• Efficient Circuit Specific Pseudoexhaustive Testing with Cellular AutomataSantanu Chattopadhyay. 188-193 [doi]
• Fault Set Partition for Efficient Width CompressionEmil Gizdarski, Hideo Fujiwara. 194-199 [doi]
• A Reseeding Technique for LFSR-Based BIST ApplicationsNan-Cheng Li, Sying-Jyan Wang. 200-205 [doi]
• A ROMless LFSR Reseeding Scheme for Scan-based BISTEmmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos. 206 [doi]
• A Fault-Tolerant Architecture for Symmetric Block CiphersMin-Kyu Joo, Jin Hyung Kim, Yoon-Hwa Choi. 212-217 [doi]
• A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW OverheadFabian Vargas, Djones Lettnin, Diogo B. Brum, Dárcio Prestes. 218-223 [doi]
• Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition SystemsFabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.. 224-229 [doi]
• Easily Testable and Fault-Tolerant Design of FFT Butterfly NetworksShyue-Kung Lu, Chien-Hung Yeh. 230 [doi]
• Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA sShyue-Kung Lu, Chung-Yang Chen. 236-241 [doi]
• Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout ConstraintsKeith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu. 242-247 [doi]
• Diagnosis Of Byzantine Open-Segment FaultsShi-Yu Huang. 248 [doi]
• Robust Space Compaction of Test ResponsesAlexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty. 254-259 [doi]
• An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS)Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri. 260-265 [doi]
• An Embedded Built-In-Self-Test Approach for Analog-to-Digital ConvertersSheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang. 266 [doi]
• Statistical Analysis of Time Series Data on the Number of Faults Detected by Statistical Analysis of Time Series Data on the Number of Faults Detected by Software TestingSousuke Amasaki, Takashi Yoshitomi, Osamu Mizuno, Tohru Kikuno, Yasunari Takagi. 272-277 [doi]
• An Analytic Software Testability ModelJin-Cherng Lin, Szu-Wen Lin. 278-283 [doi]
• Effective Automated Testing: A Solution of Graphical Object VerificationJuichi Takahashi, Yoshiaki Kakuda. 284 [doi]
• At-Speed Built-in Test for Logic Circuits with Multiple ClocksKazumi Hatayama, Michinobu Nakao, Yasuo Sato. 292-297 [doi]
• A Test Point Insertion Method to Reduce the Number of Test PatternsMasayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta. 298-304 [doi]
• A SoC Test Strategy Based on a Non-Scan DFT MethodHiroshi Date, Toshinori Hosokawa, Michiaki Muraoka. 305-310 [doi]
• Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on ChipsKazuhiko Iijima, Armagan Akar, Charlie McDonald, Dwayne Burek. 311-316 [doi]
• Manufacturing Test of SoCsRohit Kapur, Thomas W. Williams. 317-319 [doi]
• Recent Advances in Test Planning for Modular Testing of Core-Based SOCsVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen. 320 [doi]
• A Method to Reduce Power Dissipation during Test for Sequential CircuitsYoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu. 326-331 [doi]
• Test Power Optimization Techniques for CMOS CircuitsZuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min. 332-337 [doi]
• Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock DisablingKuen-Jong Lee, Jih-Jeen Chen. 338 [doi]
• A Simple Wrapped Core Linking Module for SoC Test AccessJaehoon Song, Sungju Park. 344-349 [doi]
• Testing System-On-Chip by Summations of Cores? Test Output VoltagesK. Y. Ko, Mike W. T. Wong, Y. S. Lee. 350-355 [doi]
• Test Scheduling of BISTed Memory Cores for SOCChih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin. 356 [doi]
• Effective Error Diagnosis for RTL Designs in HDLsTai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou. 362-367 [doi]
• Evolutionary Test Program Induction for Microprocessor Design VerificationFulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero. 368-373 [doi]
• Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware ModelsShahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi. 374 [doi]
• Testing Embedded Systems by Using a C++ Script InterpreterHarald J. Zainzinger. 380-385 [doi]
• Extending EDA Environment From Design to TestRochit Rajsuman. 386-391 [doi]
• Vector Memory Expansion System For T33xx Logic TesterKazuhiro Yamada, Yoshikazu Takahashi. 392 [doi]
• Integrated Test Scheduling, Test Parallelization and TAMDesignErik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng. 397-404 [doi]
• Core - Clustering Based SOC Test Scheduling OptimizationYu Huang, Sudhakar M. Reddy, Wu-Tung Cheng. 405-410 [doi]
• Test Scheduling and Test Access Architecture Optimization for System-on-ChipHuan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin. 411 [doi]
• CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power SupplyHiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo. 417-422 [doi]
• Test Time Reduction for I DDQ Testing by Arranging Test VectorsHiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada. 423-428 [doi]
• Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point InsertionShambhu J. Upadhyaya, Jae-Min Lee, Padmanabhan Nair. 429-434 [doi]