Table of Contents

• Author Index [doi]
• Referees [doi]
• Message from the Chairpersons [doi]
• Conference Organizers [doi]
• An Imaging Library for a TriCore Based Digital CameraA. Chihoub, Y. J. Bai, Visvanathan Ramesh. 3-11 [doi]
• FreeTIV Parallel Computer: Architecture and EnvironmentFrank Amiot, Edwige Pissaloux. 12-17 [doi]
• Active Computer Vision SystemDietrich Paulus, Christopher Drexler, Michael Reinhold, Matthias Zobel, Joachim Denzler. 18 [doi]
• The Acadia Vision ProcessorGooitzen S. van der Wal, Michael W. Hansen, Michael R. Piacentino. 31-40 [doi]
• Method of Moment Calculation for a Digital Vision Chip SystemIdaku Ishii, Takashi Komuro, Masatoshi Ishikawa. 41-48 [doi]
• High Speed Target Tracking Vision ChipTakashi Komuro, Idaku Ishii, Masatoshi Ishikawa, Atsushi Yoshida. 49-56 [doi]
• A VLSI Architecture for Image Sequence Segmentation using Edge FusionJinsang Kim, Tom Chen. 57 [doi]
• On Quantum and Classical Computing with Arrays of Superconducting Persistent Current QubitsPieter Jonker, Jie Han. 69 [doi]
• 2-D Object Recognition by Structured Neural Networks in a Pyramidal ArchitectureVirginio Cantoni, Alfredo Petrosino. 81-86 [doi]
• A High Speed Flat CORDIC Based Neuron with Multi-Level Activation Function for Robust Pattern RecognitionBimal Gisutham, Thambipillai Srikanthan, Vijayan K. Asari. 87-94 [doi]
• Parallel Segmentation Based on Topology with the Associative Net ModelDidier Dulac, Gilles Bertrand, Saloua Guezguez. 95 [doi]
• A Genetically Optimized Artificial Neural Network Structure for Feature Extraction and Classification of Vascular Tissue Fluorescence SpectrumsGeorge A. Rovithakis, M. Maniadakis, Michalis E. Zervakis. 107-111 [doi]
• An FPGA Architecture for High Speed Edge and Corner DetectionCesar Torres-Huitzil, Miguel Arias-Estrada. 112-116 [doi]
• Recovering 3-D Egomotion Parameters from Optic Flow: From Structural Principles to Analog ArchitecturesSilvio P. Sabatini, P. Cavalleri, Fabio Solari, Giacomo M. Bisio. 117-121 [doi]
• Space Variant Vision and Pipelined Architecture for Time to Impact ComputationFernando Pardo, I. Llorens, F. Mico, Jose Antonio Boluda. 122-126 [doi]
• Multi-Sensors and Environment Simulator for Collision Avoidance ApplicationsS. Bouaziz, M. Fan, Roger Reynaud, T. Maurin. 127-130 [doi]
• Fast Stable Matching Algorithm using Asynchronous Parallel Programming ModelF. Verdier, Alain Mérigot, Bertrand Zavidovique. 131-135 [doi]
• Fast Retrieval on Compressed Images for Internet ApplicationsMaria Grazia Albanesi, Alessandro Giancane. 136-141 [doi]
• A Scalable Affine Core for Video Object Motion CompensationWael M. Badawy, Magdy Bayoumi. 142-146 [doi]
• Implementation of the SVM Neural Network Generalization Function for Image ProcessingRoberto A. Reyna, Daniel Esteve, Dominique Houzet, Marie-France Albenge. 147 [doi]
• A System-On-A-Chip for Pattern Recognition Architecture and Design MethodologyM. Aberbour, Habib Mehrez, François Durbin, Jacques Haussy, P. Lalande, André Tissot. 155-162 [doi]
• Notacheck: A Parallel DSP-Based Architecture for Real Time High Resolution Inspection of Bank-NotesG. Coldani, L. Cotrino, Giovanni Danese, Francesco Leporati, M. Maneri. 163 [doi]
• In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-TimeNuno Roma, Leonel Sousa. 170 [doi]
• A Distributed System for Real-Time Volume ReconstructionEugene Borovikov, Larry S. Davis. 183-189 [doi]
• A Distributed Architecture for Autonomous Navigation of RobotsVito Di Gesù, B. Lenzitti, Giosuè Lo Bosco, Domenico Tegolo. 190-194 [doi]
• Study of a Parallel CBIR Implementation using MPIJosé Luis Bosque, Oscar David Robles, Angel Rodríguez, Luis Pastor. 195-204 [doi]
• Real-Time Computer Vision on PC-Cluster and Its Application to Real-Time Motion CaptureDaisaku Arita, Satoshi Yonemoto, Rin-ichiro Taniguchi. 205 [doi]
• FPGA-Based Coprocessor for Text String ExtractionNalini K. Ratha, Anil K. Jain, Diane T. Rover. 217-221 [doi]
• Compiling and Optimizing Image Processing Algorithms for FPGAsBruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins. 222-231 [doi]
• A Configurable Processor Network for Document ManagementSebastien Vagnier, Hassane Essafi, Alain Mérigot. 232-239 [doi]
• How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?Didier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani. 240 [doi]
• Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing?Marco Ferretti. 249 [doi]
• Loop Regularization for Image and Video Processing on Instruction Level Parallel ArchitecturesNicola Zingirian, Massimo Maresca. 261-269 [doi]
• Examples of Image Processing to Benefit from an Asynchronous ImplementationEric Senn, Bertrand Zavidovique. 270-279 [doi]
• Anet: A Programming Environment for Parallel Image AnalysisBertrand Ducourthial, Alain Mérigot, Nicolas Sicard. 280 [doi]
• An Array Control Unit for High Performance SIMD ArraysMartin C. Herbordt, Jade Cravy, Honghai Zhang, Calvin Lin, Hong Rao. 293-301 [doi]
• The Long And Winding Road to High-Performance Image Processing with MMX/SSEGianni Conte, Stefano Tommesani, Francesco Zanichelli. 302-310 [doi]
• Hardware Prefetching Techniques for Cache Memories in Multimedia ApplicationsRita Cucchiara, Massimo Piccardi, Andrea Prati. 311-319 [doi]
• Hardware Supported Technique for Detecting Multi-Corners In Digital ContoursAndrzej Sluzek. 320 [doi]
• Homography Based Parallel Volume Intersection: Toward Real-Time Volume Reconstruction using Active CamerasToshikazu Wada, Xiaojun Wu, Shogo Tokai, Takashi Matsuyama. 331-339 [doi]
• Handling Artifacts in Digitally Reproduced DocumentsLuigi Cinque, Stefano Levialdi, Luca Lombardi, Steven L. Tanimoto. 340-346 [doi]
• Compressed-Domain Classification of Texture ImagesBeth Wilson, Magdy A. Bayoumi. 347-355 [doi]
• Fast Stereo Matching for the VIDET System using a General Purpose Processor with Multimedia ExtensionsLuigi di Stefano, Stefano Mattoccia. 356 [doi]