Abstract is missing.
- A case for dynamic pipeline scalingJinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg. 1-8 [doi]
- A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processorJack Liu, Fred C. Chow. 9-18 [doi]
- Components for embedded software: the PECOS approachThomas Genssler, Alexander Christoph, Michael Winter, Oscar Nierstrasz, Stéphane Ducasse, Roel Wuyts, Gabriela Arévalo, Bastiaan Schönhage, Peter O. Müller, Christian Stich. 19-26 [doi]
- Efficient architecture/compiler co-exploration for ASIPsDirk Fischer, Jürgen Teich, Michael Thies, Ralph Weper. 27-34 [doi]
- Cycle-time aware architecture synthesis of custom hardware acceleratorsMukund Sivaraman, Shail Aditya. 35-42 [doi]
- An adaptive chip-multiprocessor architecture for future mobile terminalsMladen Nikitovic, Mats Brorsson. 43-49 [doi]
- Towards automatic synthesis of a class of application-specific sensor networksAmol Bakshi, Jingzhao Ou, Viktor K. Prasanna. 50-58 [doi]
- Hardware implementation of the Ravenscar Ada tasking profileMichael Ward, Neil C. Audsley. 59-68 [doi]
- Bit section instruction set extension of ARM for embedded applicationsBengu Li, Rajiv Gupta. 69-78 [doi]
- Code coverage and input variability: effects on architecture and compiler researchHillery C. Hunter, Wen-mei W. Hwu. 79-87 [doi]
- An integrated approach to reducing power dissipation in memory hierarchiesJayaprakash Pisharath, Alok N. Choudhary. 88-97 [doi]
- Embedded cache architecture with programmable write buffer support for power and performance flexibilityAfzal Malik, Bill Moyer, Roger Zhou. 98-107 [doi]
- Increasing power efficiency of multi-core network processors through data filteringGokhan Memik, William H. Mangione-Smith. 108-116 [doi]
- Cost effective memory disambiguation for multimedia codesEsther Salamí, Jesús Corbal, Carlos Álvarez, Mateo Valero. 117-126 [doi]
- Optimizing inter-nest data localityMahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Joseph Zambreno. 127-135 [doi]
- Leakage-proof program partitioningTao Zhang, Santosh Pande, André L. M. dos Santos, Franz Josef Bruecklmayr. 136-145 [doi]
- Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processorsJian-Liang Kuo, Tien-Fu Chen. 147-155 [doi]
- Control-theoretic dynamic frequency and voltage scaling for multimedia workloadsZhijian Lu, Jason Hein, Marty Humphrey, Mircea R. Stan, John Lach, Kevin Skadron. 156-163 [doi]
- Energy aware task scheduling with task synchronization for embedded real time systemsRavindra Jejurikar, Rajesh K. Gupta. 164-169 [doi]
- Scenario-based software characterization as a contingency to traditional program profilingJeffry T. Russell, Margarida F. Jacome. 170-177 [doi]
- Experience with a retargetable compiler for a commercial network processorJinhwan Kim, Sungjoon Jung, Yunheung Paek, Gang-Ryung Uh. 178-187 [doi]
- PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizationsAlex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee. 188-197 [doi]
- Wave pipelining for application-specific networks-on-chipsJiang Xu, Wayne Wolf. 198-201 [doi]
- Handling of packet dependencies: a critical issue for highly parallel network processorsStephen W. Melvin, Yale N. Patt. 202-209 [doi]
- On achieving balanced power consumption in software pipelined loopsHongbo Yang, Guang R. Gao, Clement Leung. 210-217 [doi]
- Low Power Control Techniques For TFT LCD DisplaysFranco Gatti, Andrea Acquaviva, Luca Benini, Bruno Riccò. 218-224 [doi]
- Dynamic battery state aware approaches for improving battery utilizationSung Park, Mani B. Srivastava. 225-231 [doi]
- System lifetime extension by battery management: an experimental workDavide Bruni, Luca Benini, Bruno Riccò. 232-237 [doi]
- Process cruise control: event-driven clock scaling for dynamic power managementAndreas Weissel, Frank Bellosa. 238-246 [doi]
- HW / SW partitioning approach for reconfigurable system designKarim Ben Chehida, Michel Auguin. 247-251 [doi]
- An efficient technique for exploring register file size in ASIP synthesisManoj Kumar Jain, M. Balakrishnan, Anshul Kumar. 252-261 [doi]
- Instruction generation and regularity extraction for reconfigurable processorsPhilip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh. 262-269 [doi]
- Automatic floating-point to fixed-point conversion for DSP code generationDaniel Menard, Daniel Chillet, François Charot, Olivier Sentieys. 270-276 [doi]
- Iterative procedural abstraction for code size reductionDae-Hwan Kim, Hyuk-Jae Lee. 277-279 [doi]
- Validating software pipelining optimizationsRaya Leviathan, Amir Pnueli. 280-287 [doi]
- Ensuring code safety without runtime checks for real-time control systemsSumant Kowshik, Dinakar Dhurjati, Vikram S. Adve. 288-297 [doi]
- Predictable programs in barcodesAlwyn Goodloe, Michael McDougall, Carl A. Gunter, Rajeev Alur. 298-303 [doi]
- Real Java for real time - gain and painAnders Nilsson, Torbjörn Ekman, Klas Nilsson. 304-311 [doi]