Abstract is missing.
- Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policiesFazal Hameed, Lars Bauer, Jörg Henkel. 1-10 [doi]
- ILPc: A novel approach for scalable timing analysis of synchronous programsJia Jie Wang, Partha S. Roop, Sidharta Andalam. 1-10 [doi]
- Hardware acceleration for programs in SSA formManuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack, Jörg Henkel. 1-10 [doi]
- EVA: An efficient vision architecture for mobile systemsJason Clemons, Andrea Pellegrini, Silvio Savarese, Todd M. Austin. 1-10 [doi]
- Tutorial: Methodologies and tools for embedded multisensory systems based on ARM cortex M processorsZeljko Zilic. 1-8 [doi]
- Scrubbing unit repositioning for fast error repair in FPGAsGabriel L. Nazar, Leonardo P. Santos, Luigi Carro. 1-10 [doi]
- Cyber physical systems: Systems engineering of industrial embedded systems - Barriers, enablers and opportunitiesClas A. Jacobson, Richard Schooler, Michel Laurence. 1-3 [doi]
- An efficient run-time encryption scheme for non-volatile main memoryXian Zhang, Chao Zhang, Guangyu Sun, Jia Di, Tao Zhang. 1-10 [doi]
- CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processorsVasileios Porpodas, Marcelo Cintra. 1-10 [doi]
- Power-performance modeling on asymmetric multi-coresMihai Pricopi, Thannirmalai Somu Muthukaruppan, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin. 1-10 [doi]
- Fault detection and recovery efficiency co-optimization through compile-time analysis and runtime adaptationHao Chen, Chengmo Yang. 1-10 [doi]
- Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systemsAnup Das, Akash Kumar, Bharadwaj Veeravalli. 1-10 [doi]
- Minimizing code size via page selection optimization on partitioned memory architecturesMengting Yuan, Chun Jason Xue, Chen Yong, Qing'an Li, Yingchao Zhao. 1-10 [doi]
- Global property violation detection and diagnosis for wireless sensor networksMan Wang, Zhiyuan Li. 1-10 [doi]
- Platform-dependent code generation for embedded real-time softwareBaekGyu Kim, Linh T. X. Phan, Oleg Sokolsky, Insup Lee. 1-10 [doi]
- Effective code discovery for ARM/Thumb mixed ISA binaries in a static binary translatorJiunn-Yeu Chen, Bor-Yeh Shen, Quan-Huei Ou, Wuu Yang, Wei-Chung Hsu. 1-10 [doi]
- Compiled multithreaded data paths on FPGAs for dynamic workloadsRobert Halstead, Walid A. Najjar. 1-10 [doi]
- Automatic Extraction of pipeline parallelism for embedded heterogeneous multi-core platformsDaniel Cordes, Michael Engel, Olaf Neugebauer, Peter Marwedel. 1-10 [doi]
- SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systemsPrasenjit Chakraborty, Preeti Ranjan Panda. 1-10 [doi]
- Dynamic hardware specialization-using moore's bounty without burning the chip downKarthikeyan Sankaralingam. 1 [doi]
- Exploiting phase inter-dependencies for faster iterative compiler optimization phase order searchesMichael R. Jantz, Prasad A. Kulkarni. 1-10 [doi]
- Bitcoin and the age of Bespoke SiliconMichael Bedford Taylor. 1-10 [doi]
- A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memoryThierry Lepley, Pierre G. Paulin, Eric Flamand. 1-10 [doi]
- From software to accelerators with LegUp high-level synthesisAndrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson. 1-9 [doi]
- Hybrid compile and run-time memory management for a 3D-stacked reconfigurable acceleratorLovic Gauthier, Shinya Ueno, Koji Inoue. 1-10 [doi]
- Expandable process networks to efficiently specify and explore task, data, and pipeline parallelismLars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele. 1-10 [doi]